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    What is the definition of one hot encoding?

    What is one hot encoding?

    •   Alt1st June 2005, 06:53

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    Re: One hot encoding




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    Re: One hot encoding

    suppose u have 5 states state0, state1, .., state4
    one hot encoding encodes them as follows:
    1-number of bits for encoding is number of states (5 in our case)
    2-for each state one & only one bit bit will be set as follows
    state0 => 00001
    state1 => 00010
    state2 => 00100
    state3 => 01000
    state4 => 10000



    •   Alt1st June 2005, 09:04

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    Re: One hot encoding

    As amraldo write, this use one FF per state.

    Using one-hot encoding use more FF, and more FPGA resources, but the benifit is that it can run at much higher speed.

    Suppose the following example. Imagine that at:

    State 1, you add 2 numbers.
    State 2, you substract 2 other numbers.
    State 3, you wait for some event, looping back to State 3 until event occur.
    State 4, you send the results somewhere.

    Now, this could use 2 FF to represent all 4 states (00, 01, 10 and 11). However, at the output of the FF, you will need a decoder for each of the states above. So, for state 1 (add 2 numbers), the adder hardware will first need to ensure that the FSM is in state 1, by using some logic gates to trigger when the 2 FF are '00'. Same for the subtracter, which will need some logic gate to trigger when the 2 FF are '01', and so on.

    With one-hot encoding, instead of using 2 FF, you use 4 FF, one per state. So, FF #1 will be '1' when in state 1 (the other FF will be zero). FF #2 will be '1' when in state 2 (the other FF will be zero)... and so on. This way, the hardware adder, subtracter, ... doesn't need to have a decoder at input. It do the operation as soon as the FF output a 1.

    This may first seem like both ways come to the same result, but if you look at timing, the state machine change state on clock transition. That is, the FF switch upon CLK input. However, since the one-hot encoding remove the need for state decoder, this meen that the hardware adder, subtractor, ... in the example above will output result faster (from clock transition to output result). This result in higher frequency limit for the FSM block.



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    Re: One hot encoding

    let us expand the talking:
    As far as I am aware the one-hot is the most appropriate FSM scheme, when talking about Xilinx FPGA, and when your FSM is more than 4 and up to 30-40, mainly because of two reasons you don't need to decode the states
    i.e. each state is simply a FF, this effecient usually because u contaminate the combinatorial logic at some before the FFs, yet at large state machine this might be ineffecient.
    another one-hot encoding viirtue is having a hamming distance of 2, this give u the ability to avoid false FSM state "u can detect an error and use a safe FSM scheme that manages to go to a specific state when error occur further more u can complicate the design to manage what stage on what error state", this makes one-hot very appealing to avoid single event upset SEU and very appealing in aerospace applications.
    yet at at further than 40- state machines I don't think it is effecient, up till the moment I didn't have the challenge but I believe that at very large state machine the gray code might be appealing for me because of one bit change per transition, low power consumption, less skew of stage output, might give the same area as the binary encoding still it don't provide any error recovery or detection "intuitively the hamming distance is one for the gray codes".
    So does any one worked with large FSM that can give us guidelines for this case especially error avoidance, detection and correction for very large FSM
    of course one can use other hamming codes with much larger hamming distance but I don't have until now guidelines in this area and the impact on speed / area, up until now I didn't face the challenge, in some cases I even use parallel FSMs to avoid such trap.
    does any one can give us guides?



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    Re: One hot encoding

    One hot encoding is a fsm coding style, where each state we use a new flipflop, so it is suitable for small designs as the complexinty increases with the design, But the advantage is that it is easy and error free style.



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    Re: One hot encoding

    if you want to use four state:

    one hot encoding is:

    state_1: 0001

    state_2: 0010

    state_3: 0100

    state_4: 1000


    Quote Originally Posted by manik_vivek_82
    What is one hot encoding?



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    Re: One hot encoding

    The choice to go for one-hot encoding in an FPGA depends on the state machine you want to build. An FPGA has a limited fan-in per flip-flop LUT, and a one-hot flipflop uses the following signals in the combinatorial equation for each state flip-flop:
    each previous state, all condition signals that determine to pass to that state, an all condition signals that cause it to leave that state.

    So if you have a state machine with 10 states, that are strongly linear (1,2,3,4,5...) then the logic for e.g. state 4 only depends on the state 3 signal and the conditions to go to state 4, and the conditions to leave to state 5. Independent of the # of states, if this means you have a 4-input LUT based FPGA, then you can perhaps have only one LUT level instead of more levels if you would have other encodings. For binary encoding you always have at least the width of the state (4 bits in my example with 10 states) and so you could never have a state machine with only 1 LUT level that has conditions to transition to the next state. Binary state machines need all conditions of all states for each logic equation and are therefore slower in more cases.

    Only if there are many ingoing and outgoing arrows in your state diagram and many conditions, the one hot state machine becomes less efficient than the binary because each of the N previous states has to go to a LUT input, whereas the binary encoding is compact and limited to log2(N).



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