gold_kiss
Full Member level 4
fpga demo board
Hi All,
I am developing a XC3SPQ208 Demo board. I have following questions on the same.
1. Should the demo board be in 4 layered? or 2 layer would do.
2. I am using XCF01SVO20 Flash. Is this alright? I mean does the flash match the required basic criteria.
3. M0, M1, and M2 pins of FPGA should be connected in what fashion.
4. Can all IO's banks support 3.3V?
5. Does any IO have special care to be taken?
6. 1.2V, 2.5V and 3.3V for VCCINT, VCCAUX, VCCO is the supply given to all pins respectively. In which case all IO's are 3.3V?
7. Wht is the value of Bypass cap and decoupling cap? Wht all care should be taken while designing the board? Do I need to place the caps near the power ground pin? or is it I need to place it near the regulator?
8. Any references for board design will be highly appreciated.
9. Foot print of caps and registers 1026 value needed. Also foot print and shematic of xilinx PQ208 needed.
10.
Thanks,
Gold_kiss
Hi All,
I am developing a XC3SPQ208 Demo board. I have following questions on the same.
1. Should the demo board be in 4 layered? or 2 layer would do.
2. I am using XCF01SVO20 Flash. Is this alright? I mean does the flash match the required basic criteria.
3. M0, M1, and M2 pins of FPGA should be connected in what fashion.
4. Can all IO's banks support 3.3V?
5. Does any IO have special care to be taken?
6. 1.2V, 2.5V and 3.3V for VCCINT, VCCAUX, VCCO is the supply given to all pins respectively. In which case all IO's are 3.3V?
7. Wht is the value of Bypass cap and decoupling cap? Wht all care should be taken while designing the board? Do I need to place the caps near the power ground pin? or is it I need to place it near the regulator?
8. Any references for board design will be highly appreciated.
9. Foot print of caps and registers 1026 value needed. Also foot print and shematic of xilinx PQ208 needed.
10.
Thanks,
Gold_kiss