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Spice simulation for Clock Tree & Timing Analysis

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sudhirtj

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clock tree analyst

Hi,

Does anyone know how to do the spice simulation for the clock tree and for timing analysis? This is a digital design and want to do spice simulation for clock tree, timing analysis and noise analysis.
what are the commands for this in hspice and how to look for in the result, i mean in the graphs or any such things?

Thanks in advance.
Sudhir
 

clok simulation pspice

Hi,
First the clock tree should be extracted from the design.
The spice netlist with only clock info (usually contains only only inverters and buffers) is to be obtained.
The delay between any two nodes of the netlist can be measured using the .measure statement. This is called the dynamic timing analysis.
SpiceTrack-CP, Nanosim are the special tools that can do this.
Thanks
 
Re: clok simulation pspice

Hi,
First the clock tree should be extracted from the design.
The spice netlist with only clock info (usually contains only only inverters and buffers) is to be obtained.
The delay between any two nodes of the netlist can be measured using the .measure statement. This is called the dynamic timing analysis.
SpiceTrack-CP, Nanosim are the special tools that can do this.
Thanks
Dear sowmya005
Salaam
Could you say that how can i extract spice netlist of clock tree of my design in Encounter?
I am impatiently wait to your response.

Thanks in advance.
Oveis
 

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