DFM rules explanation

Hi dear friends. I came across this concept and I would like to appeal to the skillful people with experience in real world design what DFM rules are, advantages and disadvantages and how they differ from custom set of rules?
Came across this concept recently and I have never heard about it. Searching around the web I can't find a lucid explanation that I can understand.
Thank you very much in advance.

This is a catch-all category of all the "stuff" that
has to go onto the masks to enable or improve
manufacturing yield.

It can be things like density fills and reliability
rules (generally embedded in DRC or as an option).
It can be alignment marks and level IDs (ensuring
the right masks are applied, is a manufacturing
concern).

Different elements, different concerns, but an
orderly product development flow will challenge
them all with "blessed" rules checks.

Design For Manufacruing rules are set by the process fab and they recommend using them to improve the yeild and relibilbilty of a chip.
The rules would recommend usage of straight and 45 degree angles, double via usage and metal paths than minimum, eg 0.18um path coule be 0.2um (>10% increase)

Although following minimum design rules and LVS is reasonable for product functionality demonstration, for
better manufacturability and better yield performance it is always better to follow certain good layout practices.
Those practices may not necessarily result into bigger die size most of the time.

Relaxed design rules with dimensions increased from baseline ground-rule minimums will generally
improve process and reliability yields. Minimum design dimensions should only be used to decrease
chip size or improve device performance.
3. Minimum lines and spaces increase circuit density. When circuit density is not limited by these rules,
increase the minimum line and space values by 10% to 20% as applicable during design layout. This
practice improves the product manufacturability; yields and performance by reducing interconnect
resistance and capacitance.
4. The minimum Metal overlap-of-Contact and via rules are given to increase interconnect density.
Where interconnect is not limited by these rules, relax the Metal overlap-of-Contact and via by
10%-20% as applicable during design layout. This will improve both manufacturing margins and
reliability.
5. Narrow Poly2 and COMP lines are particularly susceptible to localized increases in sheet resistance
in a salicide process. In applications where DC voltage drops are critical, avoid using narrow Poly2 or
COMP lines.
6. Since thin-gate-oxide integrity is driven by random process defects, avoid using large gate oxide
areas as decoupling capacitors. Follow the antenna ratio rules to ensure reliable gate oxides.
7. Avoid long parallel routing of intra-layer metal lines. This practice reduces coupling capacitance,
improves circuit performance and suppresses cross-talk.
8. Use top-metal as power supply, ground bus signal and global interconnects since it has the lowest
resistivity.
9. Use as many redundant Contacts and vias as possible to provide design robustness against
interconnect opens.