Synthesize new frequency (with same phase) by MMCM

Hi,

I'm going to process the output of adc in FPGA.

There is 50MHz clock output of ADC ( CLK1) which is aligned with data.

I want to make 100MHz clock(CLK2) from CLK1 without any phase difference.

The CLK2 still wants to be aligned with ADC data.



Which method is most suitable to make CLK2 from CLK1?



Thanks.

Hi,

Why don't you give full information, like schematic and exact part names?
Vague informations lead to guessing...

I guess: (not sure it relates to your application....)

I'm going to process the output of adc in FPGA.

Click to expand...

..here you talk about the data output of the ADC ... but later you don't talk about data anymore.

There is 50MHz clock output of ADC ( CLK1) which is aligned with data.

Click to expand...

Usually an ADC has a clock input...
But if an ADC has a clock output ...
* it still should have a clock input (which in your case should be provided by the FPGA)
* the clock output is for synchronizing the data output (maybe DDR style)

..if so, then
* the phase relation should be given in the ADC datasheet
* I recommend to use the ADC_clock for the interface only
* I recommend to use the FPGA_clock for data processing

I want to make 100MHz clock(CLK2) from CLK1 without any phase difference.

Click to expand...

I don't recommend this, but the usual way is to use a PLL.
"Without any phase difference" is not possible --> give a useful tolerance value.

Klaus

Thanks for your reply.

Yes.
As you told, the ADC has a clock output.
This clock is 50MHz ( 1/2 frame clock which was aligned with data).
For some reason I have to use 100MHz clock (still aligned with data) in FPGA.
This is why i want to make 100MHz clock without phase difference.

I also know "Without any phase difference" is not possible.
I wonder if there is a general way.

I don't recommend this, but the usual way is to use a PLL.
"Without any phase difference" is not possible --> give a useful tolerance value.

Click to expand...

PLL is in fact the way to do, in a FPGA family with respective resources and performance.

Time delay can be low enough to allow timing closure between CLK1 and CLK2 without extra sync logic, which is probably what you want.