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How to reduce the leak current in sleep mode

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wkong_zhu

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When the chip is in sleep mode, all digital part has no clock, but the chip has >100uA leak current, Why? how can I find the leak source, and how to reduce it?
 

Leakage is a physical feature of small geometris

You can not do anything about it on design level, You have to change
type of transistors to for instance HighVt transistors

or turn that part off, i.e. no VDD => no leakage

/Konrad
 

wkong_zhu said:
When the chip is in sleep mode, all digital part has no clock, but the chip has >100uA leak current, Why? how can I find the leak source, and how to reduce it?
Click to expand...

That isn't leakage - something is still turned on. Follow eXnol's suggestions.

Keith.
 

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