xianweng
Member level 1
Hi, everyone,
My cadence version is IC6.1.7 and MMSIM version is 13.1. I am using VCVS as delay unit (I know there are some delay component in analogLib like delayline, but there are some other strange phenomena).
The testbench and simulation results are shown in the following figures. The gain of vcvs is 1 and delay time is 1.1us. The vpulse period is 7ms, pulse width is 800ns as shown in fig2. The result of the first period is right as shown in fig3, but the second period result is wrong as shown in fig4. The rising and falling time of fig4 are 177ns, which changed significantly. And the fourth period is right.
fig1. Testbench
fig2. configuration of vpulse
fig3. The simulation of the first period
fig4. The simulation of the second period
Any hint on that?
Best regards,
xianweng
My cadence version is IC6.1.7 and MMSIM version is 13.1. I am using VCVS as delay unit (I know there are some delay component in analogLib like delayline, but there are some other strange phenomena).
The testbench and simulation results are shown in the following figures. The gain of vcvs is 1 and delay time is 1.1us. The vpulse period is 7ms, pulse width is 800ns as shown in fig2. The result of the first period is right as shown in fig3, but the second period result is wrong as shown in fig4. The rising and falling time of fig4 are 177ns, which changed significantly. And the fourth period is right.
fig1. Testbench
fig2. configuration of vpulse
fig3. The simulation of the first period
fig4. The simulation of the second period
Any hint on that?
Best regards,
xianweng