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Sigma Delta ADC Noise Floor

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babun123

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I have a DT DSM with 3rd order loop filter with CIFF architecture. In Si, the low frequency noise floor is seen to increase from the idlechannel noise floor when some input sinusoid is applied to the DSM. The amount of increase in the noise floor is proportional to the amplitude of the input applied. The noise floor doesnt change with any change in the sampling frequency of the DSM (any settling related problem should reduce with lesser sampling frequency). Also 2nd and 3rd harmonics are seen. Is it possible to understand exactly what kind of nonideality in the first integrator of the DSM is showing up as this kind of artifact?
 

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