FlyingDutch
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Hello,
I would like to ask: How to generate differential (two lines) clock from "normal" clock (one line). The clock frequency is 100 MHz. Project is written in Verilog and I am using
"ISE Webpack 14.7" (Windows10 Pro) for synthessis. My FPGA is Spartan6 (XC6SLX9 in CSG324 package) on Mimas V.2 board (Numato).
Thanks in advance and Regards
I would like to ask: How to generate differential (two lines) clock from "normal" clock (one line). The clock frequency is 100 MHz. Project is written in Verilog and I am using
"ISE Webpack 14.7" (Windows10 Pro) for synthessis. My FPGA is Spartan6 (XC6SLX9 in CSG324 package) on Mimas V.2 board (Numato).
Thanks in advance and Regards