Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Less than 50% duty cycle in two square waves shifted by 180°

Status
Not open for further replies.

DrWhoF

Advanced Member level 1
Joined
May 6, 2005
Messages
402
Helped
24
Reputation
48
Reaction score
11
Trophy points
1,298
Activity points
4,388
Two square waves shifted by 180° can have 50% duty cycle.
Is there any simple way of changing this to less than 50% but on sides of pulses so the frequency remais the same but there is short period of time between each of these waves is ON?

The reason I am asking this question is that I have a 12V-230V inverter with 10-10/230V transformer which is driven by two IRF540 mosfets. For some reason this transformer overheats and I suspect that these mosfets are turned both on for a short period of time.

Any ideas?
Thanks
 

50% duty cycle

If I got your question right... You can take two shifted waves and feed it to an AND gate and get a pulse for a duration when both the pulses are high....

Or Did I get your question wrong ? Or do you have any reasons for not doing this ?
 

50% duty cycle

"Lord Loth" is right but i think the reason of being two mosfets on is because of the current of an inductor cannot goes zero quickly!
 

Re: 50% duty cycle

You may use CD4017 chip and connect outputs 1, 2, 3 and 4 throught diodes together for driving first fet and outputs 6, 7, 8 and 9 the same way to other fet. Outputs 5 and 10 leave nonconnected. In this way you will get two nonoverlaping stearing pulses for fet's. Clock for 4017 must be 10 times the output frequency.
 

Re: 50% duty cycle

The simplest way pf shortening pulses at both edges will be to use Schmidt gates such as 4093 and connect one input directly to the clock signal whereas the other input should be connected through RC integrator. If you use R≈1kΩ and C≈4.7-10nF this should give you approximately 10µs delay. You will have to do this operation on both waves and use the remaining gates to negate both signals to achieve "shorten" positive pulses to drive the mosfets.
Can you visualize this circuit or would you like to have a diagram?
rgs
IanP
 

Re: 50% duty cycle

I don't want to stuff it up.
Drawing please.
 

Re: 50% duty cycle

You must not drive two complementary transistors with simple inverted PWM signals, because of finite time that you need to turn off transistor, which will work for some time even there is no control signal. In that case both transistors work, which makes big current (you want to short Vdd adn gnd ).
To avoid such effect betwen PWM signals should be some dead time (time for turn off transistor) in which both transistors control signals are off.
Try to search for deadband pwm....

PSoC microcontrollers have such possibility to make deadband PWM, with programable 16 bit pwm, and dead time.
 

Re: 50% duty cycle

There are more simple solutions.

You can use an IC like IR2184 from International Rectifier, or similar.
 

Re: 50% duty cycle

Attached is the drawing of a simple circuit on how to generate so called "dead time" in 2 waves shifted by 180°.
Obviously you will need 2 circuits like this (for each channel).
Good luck and regards..
IanP
 

    DrWhoF

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top