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Post simulation problem with typdelay

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billjoe

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POST SIM problem?

If in postsim
maxdelay , mindelay is ok
but typdelay fail
(typical case, some dff (of adder) hold timec annot meet SDF request).

normally speaking,

what kind of bad design style will induce this result?

Is it possible to modify synthesis script(generate a new SDF) to fix this problem?
 

Re: POST SIM problem?

Hi,

I think the cause is a large clock skew on the ff failing hold. You might also want to check your sdf file. The typical delay should be there (i.e. min:typ:max). If the typical delay is not there (i.e. min::max), then of course the simulation can give probelm. It is common nowsaday to just do min and max only.

Regards,
enghan
 

Re: POST SIM problem?

there is no need to do once ur design passes max and min simulations. max simulation will give all possible setup violations and min simulation will give all hold violation. If the design passes these two, ur design will work.

but why typ case fails?. If u increase the speed beyond ur min case passing speed, u will fail as far as hold violations are concerned.

Added after 2 minutes:

i forgot to tell u one more thing.

It is possible to do re-synthesis to fix hold violations. in synopsys u can do incremental synthesis using set_fix_hold. This will fix hold violations. First check ur design with STA.
 

Re: POST SIM problem?

Please check timing violations in Back End flow, then think of re synthesis.
 

POST SIM problem?

I think it is design bug. You can debug with the failure simulation to find it out, though it is difficult to do so.
 

Re: POST SIM problem?

perhaps it is caused by asynchronous interface signals.



billjoe said:
If in postsim
maxdelay , mindelay is ok
but typdelay fail
(typical case, some dff (of adder) hold timec annot meet SDF request).

normally speaking,

what kind of bad design style will induce this result?

Is it possible to modify synthesis script(generate a new SDF) to fix this problem?
Click to expand...
 

POST SIM problem?

u can do it at the backend of the flow, modify those error by layout design.
 

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