thomas.whatsoever
Newbie level 2
Hello,
I synthesized a design with Synopsys' Design Compiler and want get some statistics about the synthesized netlist. In particular I am interested in the number of stages/sequential cells from a flop-flop's output to the chip output. My idea was to get the path from the flip-flop to the output and counting the sequential cells in between, but all the path commands (like all_fanout, all_connected or report_timing) only work from one sequential cell to the next one. Would you have an idea to get this information?
Best regards,
Thomas
I synthesized a design with Synopsys' Design Compiler and want get some statistics about the synthesized netlist. In particular I am interested in the number of stages/sequential cells from a flop-flop's output to the chip output. My idea was to get the path from the flip-flop to the output and counting the sequential cells in between, but all the path commands (like all_fanout, all_connected or report_timing) only work from one sequential cell to the next one. Would you have an idea to get this information?
Best regards,
Thomas