eexuke
Full Member level 4
designware foundation (dwf) library
Dear all,
If I describe modulo operation in verilog, such as "a <= b % c",how can the synthesis tool help me to turn this into hardware? I think it is pretty hard for implementation if c is not equal to the power of 2......
Many thanks in advance!
Dear all,
If I describe modulo operation in verilog, such as "a <= b % c",how can the synthesis tool help me to turn this into hardware? I think it is pretty hard for implementation if c is not equal to the power of 2......
Many thanks in advance!