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I have to compare 2 signals (A and B) in VHDL and have to find out if signal A is leading then increment counter and if A is lagging then decrement counter.
Re: How to find out which signal is leading and which is lag
try to sample both of them with a clock(at rising and falling edges), then compare their values to know which of them have chnge its value b4 the other.
Re: How to find out which signal is leading and which is lag
You have to use a clock frequency such that clock period is less than the phase lead/lag time of these signal. after that sample both the signal at rising edge of the clock and whichever signal is high, put a counter and make it lag .. slwoly u will be able to match phase of both...
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