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phase aligning in PLL

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coramdeo

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Hi everyone.

I 'd like to design a PLL for frequency multiplication. I want the multiplicated output of VCO to align the input signal. However, since the output of VCO propagates through the divider, the output of VCO cannot align the phase of the reference signal. How can I solve the problem?

regards
 

if the PLL in lock state which mean the two frequencies "inputs of the phase detector"
if they are not align this depends on the phase detector type
some types give zero error when they have phase shift by 90 degree
1/4 cycle in time
or the pll u designed have a static phase error so u need to modify the type make it type II pll to cancel the static phase error
 

Usually I put a dummy delay in input clock to match delay for divider.


Yibin
 

There is an easy way to achieve zero phase error that is to use "Zero dely buffer" ic. It's a common device available from some manufacter such as ICS, Cypress.

If you wanna design one by your self, then you have to considering the addtional phase error between the reference divider and output divider.

An useful way to solve this problem is to add a "delay line" to make output phase match to the input singal.

Good luck!
Wenye
 

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