Current integrator's input noise

Hello. I have a question about ‘Current integrator’s input noise’.
I use a typical current integrator structure using single-ended amp, switch and capacitor. (left fig.)
The thing is if external noise is induced in the ‘Current input (-)’ or ‘VREF node (+)’, the integrator output fluctuate greatly and the error becomes very large.
Therefore, I’m trying to apply the pre-processing circuit which can attenuate the external noise. (right fig.)
In my opinion, can I use the ‘Current buffer circuit’ for the current input node and the ‘Unity gain buffer’ for the VREF node to reduce the influence of external noise?
It would be a great help if you let us know similar experiences or references.
Thank!

Hi,

Noise is considered to be AC. Pure noise will cause not much error, because it is poitive and negative and compensate itself after some time.

What really causes error in an integrator is "offset". Offset voltage ...and (because of your circuit) "bias" current.
(The current through the reference circuit doesn´t matter here)

An additional input stage makes things worse. Both: noise and offset.
Maybe an intelligent offset compensation circuit .. but in this short time I have no idea how to build one.

--> I recommend to use good OPAMPs with low bias current an low offset voltage.
And for sure good analog switch, good foil capacitor and an PCB layout with guard rings.
If you use wounded foil capacitors there may be a marking for the outer foil connection. --> connect this to the OPAMP output.

Klaus

Indeed, an integrator is one of those opamp circuits which require a precision opamp, both with low Input bias, and low current and voltage offsets.

Your reference must be also low noise.....don't use a zener here!

Finally, it is customary to use a very large value resistor in parallel with the capacitor. This can be as large as 10 or 20 Meg.

Without a specification for input signal and integrator, it's just small talk.

One remark, if the input is fed by a current source, Vref noise is forwarded to the output with unity gain and won't actually hurt. More generally speaking, an exact circuit analysis is suggested.

Hi, Klaus.
To begin with, thank you for your sincere advice.
I think it is necessary to explain the application that uses this integrator.
In this application, the integrator's absolute output is used and the repeat deviation(difference) of the output is one of the important performance.
For example, if the difference between the 1st mear.out and the 2nd mear.out is large (about 20mV or more), an error will occur.
Of course, by increasing the number of repetitions, the noise is reduced a lot, but it is difficult to realize due to the time constraints of the application.

Hi, schmitt.
To begin with, thank you for your sincere advice.
I have some questions about your advice.
First, I wonder what role the parallel resistor used in the integrator.
Also, I want to know if 10~20 mega resistors can be integrated in CMOS integrated circuits.

Hi,

about 20mV or more

Click to expand...

Useless information without complete schematic, circuit information, source information and timing.

--> 20mV may be a huge deviation when you use a 100uF capacitor and and integration time of 1us.
--> 20mV may be very small if you use a 10pF capacitor and an hour of integration time.

Klaus

In the DC condition the feedback capacitor offers infinite resistance and so the integrator circuit will be like an inverting opamp amplifier with infinite feedback resistance (Rf = ∞).
An amplifier with Rf=∞ would give a voltage gain of Av=∞.

In practical terms, no real-world opamp has infinite gain, but nevertheless has a very large gain.....any small input offset voltage will get amplified by this gain and there will be an error voltage at the output.

This problem can be mitigated by adding a feedback resistor Rf parallel to Cf , which will bound the DC gain to a lower value.

I'm no CMOS process expert, but I don't think that you could integrate such a high valued resistor.

Hi,

Feedback resistor or not:
I tend to say, that I'd not use one in this case. This case is, because you have a "reset" mechanism.
Without the resistor you get a more perfect integrater output, with the resistor the output becomes distorted somehow.
All the resistor current causes an error in the output signal. The amount of the error depends on the input signal, and therefore it can'be calibrated out by software.

Klaus

Hi, Klaus.
20mV is about 1% error. (Vrange=0~2V, C=10pF, Time=20us, Iin=0~1uA)
Also, integrator drives over a 300pF external load. I think the integrator output can be amplified by Cload/Cfb ratio while integrating phase. Am I right?
Therefore, I considered to apply a current buffer to reduce the load effect. What do you think about these load conditions?

Hi, schmitt.
Thank you for a detailed description. I fully understand the role of the parallel resistor used in the integrator.

Hi,

with that values:
* How precise is your timing? (reset switch .. to read out of integrator value)
* What OPAMP do you use? you need a fast OPAMP, and it needs good stability to avoid ringing.
* What about the noise of the input source?
* what about the injected charge from the analog switch?

Again the request for the complete circuit with complete informations. Please don´t waste our time.

Klaus