Problem with SRAM: big capacitor effect appears

Big problem in SRAM?

In write SRAM condition
find all the Column(the same word line)bit seem to be influenced.
(EX: word line =2, write bit line 5 =1, (2,5)=1,
then if (1,4)=1,(2,4)=0 , when write (2,5)=1you will find (2,4)=1) and (2,5)=1.
if write (2,5)=0 , still find (2,4)=1) and (2,5)=1.
==> seems (2,4) been influenced by neighber cell(when word line is selected)

but if delay the write cycle (#100 ms) speed (nCS(chip select) width is the same , but delay period between two nCS)
(2,1),(2,2),(2,3),(2,4) will not be influenced by write (2,5),
delay the write speed everything is OK(but need delay 100ms ==> too long) , so I think the SRAM circuit is OK, but seems has some very big capacitor
effect appear in my SRAM.


Is any SRAM master can guess what happen to my SRAM???

Re: BIG PROBLEM in SRAM?

I am not a SRAM master... But I have seen certain SRAM designs....
I can help you incase u can answer following query...
1. Is the memory selftimed....
2. While writing in 5 only 4 changes or 3,2,1 also changes...
3. Writing of 1 is problem or 0 is also the problem... say 1 creates problem at 4 so do the 0 also creates problem at 4...
4. Please also tell whether the contents of other cell changes irrespective of there previous data ...

BIG PROBLEM in SRAM?

tks to nitu

1. Is the memory selftimed....
==> no
2. While writing in 5 only 4 changes or 3,2,1 also changes...
==> yes , but not write 1 ,then 1,2,3,4, all become '1'

3. Writing of 1 is problem or 0 is also the problem... say 1 creates problem at 4 so do the 0 also creates problem at 4...
==> both '1' or '0'

4. Please also tell whether the contents of other cell changes irrespective of there previous data ...
==> I do a test(wordline, bitline)
(6,1,)=0 ,(7,1)=0
(6,2,)=0 ,(7,2)=1
(6,3,)=1 ,(7,3)=0
(6,4,)=1 ,(7,4)=1
the write (7,5)=1
then find
(6,1,)=0 ,(7,1)=0
(6,2,)=0 ,(7,2)=0
(6,3,)=1 ,(7,3)=1
(6,4,)=1 ,(7,4)=1
(3.3V)
but when delay #100ms
between write (1,5),(2,5),(3,5),(4,5),(5,5),(6,5),(7,5)
(the write order is wordline++ , bit)...
then the sram is OK
so it's a little like every bit will be influenced by the same bit line data
but it's previous bit or first bit or next bit(in the same bit line)
I am not sure, only I can make sure(guess) is not influenced by the data I write( 1 or 0)?

Big problem in SRAM?

Can you explain more on the physical structure of the SRAM cell. Is it 4T or 6T cell. For 6T cell, I never see such thing. By the way, have you calculate the substrate resistance and the leakage path of the storage node.

If you checked that your word and column decode have no problem. You have better check the SRAM cell.

Re: Big problem in SRAM?

Hi.
The above observations only suggests (as you have said earlier) that problem might due to be of very big capacitor (VDD and GND mesh capacitances) and very high resistance which is connected to vdd and gnd rail.
I do not konw how have routed your chip or memory but it appears that during write a VDD capacitor of the SRAM module get discharged and now it needs quite some time to get charged back.
In case you do not allow it to get changed fully you may expect some SNM issues which is visible in your case.

So I would suggest check resistance of the vdd connected to the mesh.
Also I have certain doubt about the input mesh of the MEMORY MODULE. This internal mesh might not be well laid and we can expect very high IR drops...

Big problem in SRAM?

i will desgn the sram who can tell me some basic book about it

Re: Big problem in SRAM?

dasong said:

i will desgn the sram who can tell me some basic book about it

Click to expand...

A very good book:
Analysis and Design of Digital Integrated circuits by David A. Hodges