Fast, low power sample and hold circuit

Hello, I want to design a sample and hold circuit (discrete components, not IC) but I'm having trouble combining fast and low power...
I would like an acquisition (sampling) time of a few ns, hold time (steady data) for at least 300ns and current consumption below 1mA.
Any suggestions?
Thank you in advance!

I think you will find it very difficult, if not impossible, to meet your requirements with discrete parts.

The fastest would be an open loop (switch + C)
sampling but this demands that the source be low
impedance and fast settling itself (step-load from
C-switch) and the destination be very high Z. The
hold time / droop depends on C and Zout. Sample
settling time, on C and Zin (and any upstream
settling behaviors).

A JFET can be an OK sampling switch but is tricky
to drive well (although I have designed S/H ICs
using JFETs and BJTs, at my level this is all "discretes"
as you purport to want, no ICs inside the IC). You
might want to look at some of the "chips" that are
(say) two matched pairs, NMOS and PMOS, all pinned
out independently so you could lash up a CMOS
sampling switch (driven by whatever discrete gate
control kludge you like). Of course a CD4066 CMOS
switch quad would take care of all that too, neater.

Long hold times (like, I was on the hook for 20uS)
likely want a buffer amp with a very high Z input
(I went with designing a JFET-input op amp). The
amp is put inside the sample loop to "kill" Vio, at
the cost of some significant sample settling time.
Residual hold-pedestal from sample switch charge
pumping is an issue with all S/Hs and the discrete
solution is probably going to be bad for this since
you have no authority over individual devices size /
capacitance match, only whatever comes in the tube
from Digi-Key.