Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] vhdl FSM lockout, lazy approach to fix

Status
Not open for further replies.

wtr

Full Member level 5
Joined
May 1, 2014
Messages
299
Helped
29
Reputation
58
Reaction score
25
Trophy points
1,308
Activity points
4,108
Hello all,

I have a situation where every state bar one requires a specific condition. I want an elegant solution to avoid having to place my condition in every state. The stuff below works, but it feels messy.


Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
if rising_edge(clk) then
  if rst then
    --stuff
  else
    --default signal assignments
    if majority_of_the_time_condition then
       case state is
          when 1 => do_stuff <= y; state <= 1;
          when 2 => do_stuff <= x; state <= 3;
          when 3 => -- majority condition statement doesn't apply;
       end case;
    end if;
    if state = 3 then
      do the stuff on this clock like padding
    end if;
  end if;
end if



The less messy, but requiring more typing method is below


Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
if rising_edge(clk) then
  if rst then
    --stuff
  else
    --default signal assignments
    
       case state is
          when 1 => if majority_of_the_time_condition then do_stuff <= y; state <= 2; end if
          when 2 => if majority_of_the_time_condition then do_stuff <= x; state <= 3; end if
          when 3 => do the stuff on this clock like padding
       end case;
    end if;
  end if;
end if



Since I'm absurdly lazy, I want the first solution because it requires less typing, but it feels wrong. I fear the synthesis would create a gated clock fsm. Does anyone have any recommendation for good spell design?

Wes
 

the thing about FSMs is that you want to make sure synthesis tools see them and optimise accordingly. the first code snippet is not a typical FSM template, results might be good, but you are relying on the tool for something silly.
 

Writing readable code is an essential requirement, particularly when working in teams. I would choose the straightforward first style, or something similar and trust on the tools intelligence.

Why don't you check yourself and compare the gate level netlists?
 

VHDL allows process local variables. This is very useful if "majority of the time condition" has multiple terms. Then it ends up looking like case 1, even for complex expressions.

This code looks mostly fine to me though. There are some people who will put only state-change logic inside of the switch, and then have output logic in another structure. Without the actual code, it is hard to give an informed decision though.

I have a rule that if I feel I'm making a decision that makes the code "unclean" that I will add a comment to say that it is intentional. I will explain the intent and why the coding style provides a benefit. This allows you to explain why you did this, and readers can determine that you didn't just make a mistake while writing the code. A year later, you'll also know why you did something that (even as you are writing the logic) looks like a logic error. It also forces you to be honest -- you can't "design by simulation" when you have to provide an explanation. It also forces you to avoid being dangerously creative as you have to do more work to write weird code.

I also suggest finding a good editor. I typically don't care about typing and code length because I make rigorous, structured use of marker-based code-folding. I consider this feature to be as necessary as syntax highlighting.
 

What editor do you use VGoodtimes
 

I use vim. However emacs is also capable of this. I've been told notepad++ can do this, but I've never gotten it to work. Some other editors have a vim mode that is similar to vim but isn't perfect.

For vim, just have "set foldmethod=marker" in your vimrc. I don't actually know what the emacs settings are for this. I know that they have existed for a decade though.


With marker based code folding you get:

Code:
--{{{ section name
(a process or instance and then a few lines of code related to it)
--}}}

becomes:

--{{{ section name ---------------------

You can rigorously apply this to all logical sections of a file -- even if they are only one line. A section should be based on logical connection to the design, not length. As a result, anything in the design is inside a folded section -- even if only 1 line. Really, if a section is ONLY 1 line there is nothing wrong with noting the importance or uniqueness of that line within the file. If you do this, all internally developed files will be opened in a "table of contents" mode. It is actually an amazingly useful concept.
 

Notepad++ does codefolding by default without having to add extra markers. I never use it though. It folds on brackets, comments and keyword...end blocks.
 
Last edited:

I agree -- syntax based code folding doesn't line up to VHDL/Verilog use cases.

I've found that most developers add section lines to their code already. eg:
Code:
--------------------------------------------------------------------------------
-- Input Buffer

And then there would be an instance and a short process or a few assignments to describe the logic section for "Input Buffer". This softly formalizes the idea of a logical section of the code. If there is a style rule that all code be in a section, then you get a table of contents view of the file. This makes it amazingly easy to navigate and allows new devs to get a quick idea of what a file does just based on these section headers.

This works best when the entire team has vim/emacs, but the markers don't cause any harm to notepad++ users. It is just that other people will mess up the manual folds as they don't use them. That is a minor annoyance.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top