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BRAM Synthesis error - Xilinx ISE 14.7

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DeepikaA

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Hi,

I am trying to synthesis verilog code for register file (using BRAM primitive RAMB16BWE_S36_S36) on spartan-3A board using ISE 14.7.
But I am getting an error
ERROR:Xst:2009 - Model 'RAMB16BWE_S36_S36' has different characteristics in destination library. The user component name 'RAMB16BWE_S36_S36' conflicts with the library primitive name 'RAMB16BWE_S36_S36'.

I have checked the simulation primitive definition for RAMB16BWE_S36_S36, it is matching with my BRAM instantiation and register file is working properly on simulator.
Can you please tell me the reason for this error and how to resolve this error.

Thanks.
 

Maybe it is a trivial error somewhere, I can only guess!

This is from a similar Xilinx Answer Record:
When you instantiate components from a Xilinx or user library, be sure to match component names and pins exactly. Verilog is case-sensitive, and if the case of the module name in your instantiation does not match the case of the module declaration, this error will occur.
 

Do not include a component declaration in your design. AFAIK it is already included as part of one of the libraries you included. Hence the error about a conflict. In the future it is advisable to include your code, so noone needs to guess.
 

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