Timing constraint file

How to calculate the delay after layout generation( post layout) in combinational circuit multiplier design in cadence soc encounter. How to give clock in timing constriant file in combinational circuit design . I want to see area, power, delay after layout
ram

ragramya75 said:

How to calculate the delay after layout generation( post layout) in combinational circuit multiplier design in cadence soc encounter. How to give clock in timing constriant file in combinational circuit design . I want to see area, power, delay after layout
ram

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dear lord, you are lost.

you give a clock constraint using an SDC constraint file
you can get area with report_area, delay with report_timing, power with report_power. very very simple.

ragramya75 said:

How to calculate the delay after layout generation( post layout) in combinational circuit multiplier design in cadence soc encounter. How to give clock in timing constriant file in combinational circuit design . I want to see area, power, delay after layout
ram

Click to expand...

sir

whether the post layout power is higher than prelayout power if we include timing constraint file(with clock signal present)? I am designing a reconfigurable multiplier block.
If I am comparing with the traditional multiplier circuit without a clock signal, my post layout power is almost similar to traditional multiplier blocks eventhough my prelayout power is much less than them? Then how can I compare my design

Doubts regarding delay

Hi
how to calculate delay after synthesis and post layout generation in rtl compiler and soc encounter from cadence. Is the delay can be taken as the arrival time of the clock from report timing or any other method to calculate delay. If anybody knows, reply me and it is required very urgent
ram

Re: Doubts regarding delay

ragramya75 said:

Hi
how to calculate delay after synthesis and post layout generation in rtl compiler and soc encounter from cadence. Is the delay can be taken as the arrival time of the clock from report timing or any other method to calculate delay. If anybody knows, reply me and it is required very urgent
ram

Click to expand...

if it is so urgent, perhaps you should have checked the manual? how can you use a logic/physical synthesis tool without knowing how to do a report_timing and what it means?! mind boggling.