coshy
Member level 4
Hi..
Now I'm trying to implement the simple verilog file.
and I run as "ncverilog +access+wrc top.v"
and there is no warning and error.
but can't find mem register in the simvision.
I can't understand this, how can I see the mem (memory) register in the simvision?
the other register which is not memory type is showing as well in the simvision.
but just only memory type register doesn't see in the simvision.
what am I supposed to do?
Now I'm trying to implement the simple verilog file.
Code:
module top();
reg [7:0] mem[127:0];
...
initial begin
repeat (46000) @(posedge wr_clk);
$finish;
end
...
initial begin
$shm_open("./wave");
$shm_probe(top,"AS");
end
...
endmodule
and I run as "ncverilog +access+wrc top.v"
and there is no warning and error.
but can't find mem register in the simvision.
I can't understand this, how can I see the mem (memory) register in the simvision?
the other register which is not memory type is showing as well in the simvision.
but just only memory type register doesn't see in the simvision.
what am I supposed to do?