kramper
Newbie level 3
Hi,
I would like to know how to design the PLL with XOR gate PD in simulink.
Attached is my simulation block. At high input frequency (ex:30MHz) the system is locked, however at lower frequency (ex:100Hz), the system is not locked. Is there any mistake in my model? can someone give advice on this. Thanks
I would like to know how to design the PLL with XOR gate PD in simulink.
Attached is my simulation block. At high input frequency (ex:30MHz) the system is locked, however at lower frequency (ex:100Hz), the system is not locked. Is there any mistake in my model? can someone give advice on this. Thanks