Why do you need to route clock separately in clock tree sysnthesis?

Why do you need to route clock seperately

Why do you need to route clock seperately

Re: Why do you need to route clock seperately

Hi,

Please ask complete questions. Give us enough informations what you are talking about.
Don't expect a more detailed answer than your question.

I'm not sure if you are really taking about IC inside?

What clock are you talking about: frequency, logic level, trace length...

There are many topics around clock routing:
* capacitive / inductive coupling to other signals
* the other way round
* clock jitter, precision
* clock for analog or digital circuits
* EMI, EMC issues
* clock delay
.....

Klaus

Re: Why do you need to route clock seperately

iam asking about cts

Re: Why do you need to route clock seperately

Does cts mean clock tree synthesis?

Re: Why do you need to route clock seperately

yes sir, i want know the Why do you need to route clock separately in clock tree sysnthisis?


its doing separately r at atime what happens did same time and separarately?

Re: Why do you need to route clock seperately

I suspect two things.

One, that the folks in the ASIC (digital) sections would
be of more use to you.

Two, that maybe it has to do with the clock being a
(or the most) critical timing resource, its chip-wide
consistency is important enough to give its routing
and loading priority over data and control signals.
If the P&R tool can't handle it (and making it try,
while doing all the "other 99%", would be asking a
lot and leaving a lot to chance or the competence
of the tool and its operator) then maybe the P&R
can at least be taught to respect a specially built
clock network's cells and routes, leave it alone and
give it some space.

Clock uncertainty has to be accommodated in the
timing analysis / closure. Squeezing it out leaves
more slack for the rest of the mess.