understanding basics of PLL

Elementary basics about PLL. When PLL is locked, the error is zero and VCO should not generate any frequency. But I read somewhere that error becomes constant after locking condition. I do not understand how?

Hi,

the error is zero

Click to expand...

What error is zero?
And why should it genereate no output frequency?

Those "general" statements are difficult to discuss.
--> Please post a datasheet/application note/ document/circuit .. or anything else, so we can discuss about it.

Klaus

This question is not pertaining to any datasheet but philosophy of PLL. I was referring to the link
https://www.radio-electronics.com/i...l-synthesizers/phase-locked-loop-tutorial.php. I found the following statement

"When the PLL, phase locked loop, is in lock a steady state error voltage is produced. By using an amplifier between the phase detector and the VCO, the actual error between the signals can be reduced to very small levels. However some voltage must always be present at the control terminal of the VCO as this is what puts onto the correct frequency"

Can you explain what the above statement means?

I think I know what Garimella means but it isn't correct.

The 'error' I think is the 'error voltage' from the phase discriminator. An error voltage of zero, meaning it is not changing, tells you the PLL is locked and not adjusting to the input condition. An error voltage is produced when there is a mismatch between the phase of the reference and the input signals and it is usually used to adjust the input signal so it matches the reference. Think of it more as 'correction voltage' rather than error voltage. Only if no correction is needed is the voltage zero.

A VCO that doesn't generate any frequency by definition isn't an oscillator at all!
Usually the error voltage is used to tune the VCO, it's the 'V' in VCO. The intention of a PLL is to adjust the VCO so it matches the reference frequency at the input to the phase discriminator (there could be other circuits between the VCO output and PLL input) by producing a voltage, (the error voltage) to correct any difference between them.

Brian.

You need to specify the type of phase/frequency detector and loop filter to discuss the details of PLL behavior.

In a typical PLL with PI loop filter, the phase error in locked state is about zero. Due to the high (ideally infinite) integrator gain, the loop can maintain the VCO tuning voltage without static phase error.

As KlausST mentioned "VCO should not generate any frequency" is wrong. VCO generates constant frequency in locked state.

Hi,

Without a dedicated circuit we can only guess.

Maybe you think that zero VCO input voltage means zero output frequency. But this often is wrong. Instead one should design the PLL input voltage range to the desired output frequency range.
Example: If you want to generate 50MHz VCO ouptut frequency, then you may design the circuit that it outputs 45MHz ... 55MHz with full VCO input voltage range.
--> read datasheets and application notes.

Maybe you mean that zero frequency error outputs zero phase detector voltage. This often is not true. Often it outputs VCC/2.
--> read datasheets and application notes.

Klaus

This means at error equal to zero, VCO still produces some frequency say X Mhz. Now as the input frequency changes to Y, the loop adjusts the frequency to approach Y. But at Y, error is zero and does loop to revert back to frequency X? How does it lock iteself to new frequency change?

You'll want to analyze how a reference frequency step is actually performed instead of discussing abstract statements.

Of course the phase error can't be constantly zero during the frequency step and the VCO can't track the frequency change instantly.

My suggestion is to read detailed tutorials and text books about PLL analysis and design thoroughly, not just the headlines and brief explanations.

I guess the author talks about "Dead Zone" phenomena.In this zone even the PLL is locked, there is always a small phase error that Phase Comparator is not able to sense.

FvM said:

My suggestion is to read detailed tutorials and text books about PLL analysis and design thoroughly, not just the headlines and brief explanations.

Click to expand...

Or better still, purchase a low cost 4046 and some passive components. Use a sample circuit from the datasheet.
On a Proto board, assemble the circuit.
Feed it from a variable function generator or clock source -it can be something as simple as a 555 with a variable resistor.
Now on a two channel scope, monitor both signals simultaneously. Trigger from the variable clock source.


If you have a 4-channel scope it is even better, because then you can also monitor the phase pulses coming out from the phase comparator and the VCO's control voltage (after the buffer!)

Now.....Play around changing the frequency while observing the scope. You'll learn a lot about PLL in a few minutes.

**EXTRA BONUS**
Utilize the 555's pin 5 to add modulation.