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How does Design Compiler work Internally

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What algorithm is applied to convert RTL into basic gate representation? For example how is this code synthesized step by step:

always@(posedge clk)
case(select)
4b'0000: out = input1 +input2
4b'0001: out = input1 -input2
 

you are asking us to summarise years and years of research of logic synthesis.

essentially, the tool looks for templates to identify what you are trying to do. once the tool knows where your flops are, the rest boils down to representing combinational logic as some form of graph. this graph is matched against a library to do mapping. kind of. it is much more complicated than that.
 

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