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Conversion speed of adc

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luckybrahmi

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Hi,

I am designing a 4-bit Flash ADC without any clock for the comparator. And the comparator is working till a 1Ghz sine wave input. So, what is the conversion speed of this ADC?
 

Are you doing a new state of the art design in ASIC or just using special components ? The question seems too vague to get a straight answer, but generally speaking its design specifications seems almost infeasible.
 

It's the speed at which you fail the first of many ADC
accuracy specs. I recommend you look at the definition
of ENOB, implement the tests that show the elements
of it, call your goal 3.5 bit accuracy at speed (as 4.0
would be a fantasy) and grind out the characterization.
 

It's the speed at which you fail the first of many ADC
accuracy specs. I recommend you look at the definition
of ENOB, implement the tests that show the elements
of it, call your goal 3.5 bit accuracy at speed (as 4.0
would be a fantasy) and grind out the characterization.

Can you tell me how can I find the ENOB on cadence virtuoso tool?
 

I doubt you will find any such "canned" analysis. ENOB
@ speed cares about settling time, the low-overdrive
prop delay of your ladder comparators, various detractors
and you have to challenge the design appropriately, to
see. One design might be limited by raw comparator delay,
another by harmonic distortion, and so on - also depending
on the application "care-abouts" (which, do you know?).
One application might want to see you do a Fourier on a
fundamental sine wave input, and give THD and intercept-
points type answers; another might just want to see no
missing codes at speed on a series of worst case from:to
input steps. In any case your ENOB is the rollup of many
approaches to analysis, grounded in an application scheme.

There's much info on this, especially from online university
course materials. I am no kind of expert, in comparison.
 

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