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STI role in LATCH UP

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hetirajhimanshu

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How Shallow trench isolation blocks the triggering mechanism of latch up? Please give the answer in detail, related to device physics?
 

It does not.

It makes some of the paths longer and you'd hope it
raises the trigger voltage and holding current but "hope
is not a strategy". You still need close-in well ties ("taps")
to do the shunt job, complementing the series (STI).

STI is just the modern successor to LOCOS. Neither
is foolproof (as many engineering fools now selling
real estate can attest).

There are many, many, many presentations on latchup
mechanisms, the 4-layer structures that are the root of
it, mitigation / suppression methods and so on out there
on the Web. Just a quick look and a gut understanding
of how SCRs are made and work, should show you that
STI is unable to kill a standard CMOS technology's
parasitics. Just drive them underground - staking them
through the heart is the device designer's, groundrules
architect's, layout person's job.
 
It does not.

It makes some of the paths longer and you'd hope it
raises the trigger voltage and holding current but "hope
is not a strategy". You still need close-in well ties ("taps")
to do the shunt job, complementing the series (STI).

STI is just the modern successor to LOCOS. Neither
is foolproof (as many engineering fools now selling
real estate can attest).

There are many, many, many presentations on latchup
mechanisms, the 4-layer structures that are the root of
it, mitigation / suppression methods and so on out there
on the Web. Just a quick look and a gut understanding
of how SCRs are made and work, should show you that
STI is unable to kill a standard CMOS technology's
parasitics. Just drive them underground - staking them
through the heart is the device designer's, groundrules
architect's, layout person's job.

i have already understood the term latch up, its cause, mechanism and remedies. But I got stuck at one point, I read in wikipedia that

It is possible to design chips to be resistant to latch-up by adding a layer of insulating oxide (called a trench) that surrounds both the NMOS and the PMOS transistors. This breaks the parasitic SCR structure between these transistors. Such parts are important in the cases where the proper sequencing of power and signals cannot be guaranteed, such as hot swap devices. REF : https://en.wikipedia.org/wiki/Latch-up

I could not understand the last statement .... proper sequencing.... hot swap devices. Will you please elaborate it ?
 

Deep trench isolation on SOI material completely isolates
transistors. STI is Shallow, not complete.

Hot swap means you want to plug something in with
power already on. This will also include live signals and
loads. They may be applied in almost any order. Pins
pulled hard below ground (Psub) or above VDD (Nwell)
can trigger an SCR path. The manufacturer would prefer
to not design for every pin-pin combo (even if possible)
but to simply say "don't do that, or it's your problem".
That's "proper supply and signal sequencing", which is
a luxury somebody else has to provide. For applications
that must withstand broader challenges, you address
isolation with better (for that) technology and maybe
some circuit tricks like body-blocking / body-pulling
circuitry to keep the diode conduction paths under
control as well, since now you'd have isolated device
bodies to play with. '
'
You -can- make a chip latchup immune without SOI.
Thin epi, degenerately doped handle, guardrings
instead of sparse tap contacts, and you're about there
as long as you don't miss a spot. But some jobs just
can't be done with a bazillion diodes every which way,
just waiting to put in their two cents. Then it's SOI of
some sort.
 

Deep trench isolation on SOI material completely isolates
transistors. STI is Shallow, not complete.

Hot swap means you want to plug something in with
power already on. This will also include live signals and
loads. They may be applied in almost any order. Pins
pulled hard below ground (Psub) or above VDD (Nwell)
can trigger an SCR path. The manufacturer would prefer
to not design for every pin-pin combo (even if possible)
but to simply say "don't do that, or it's your problem".
That's "proper supply and signal sequencing", which is
a luxury somebody else has to provide. For applications
that must withstand broader challenges, you address
isolation with better (for that) technology and maybe
some circuit tricks like body-blocking / body-pulling
circuitry to keep the diode conduction paths under
control as well, since now you'd have isolated device
bodies to play with. '
'
You -can- make a chip latchup immune without SOI.
Thin epi, degenerately doped handle, guardrings
instead of sparse tap contacts, and you're about there
as long as you don't miss a spot. But some jobs just
can't be done with a bazillion diodes every which way,
just waiting to put in their two cents. Then it's SOI of
some sort.

I am totally confused now, can u please put your thoughts in a much simpler way ? I could not get even a single bit of what you explained. Sorry for the inconvenience.
 

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