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Variable Frequency PWM to Analog Circuit?

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eraycanli

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Hello,

I need to convert a PWM to analog signal. But the issue is, frequency of PWM may change. So, RC-filter option is not preferred. What kind of circuitry would be appropriate for this?

By the way, there exists an IC named LTC2644, which operates exactly as I want, but not meeting my frequency requirements (5 to 500Hz frequency PWM) :/

Thanks in advance! Eray.
 

Hi,

What exactely is your target?

You want to convert duty_cycle to analog?

What are your input signal levels?
What is your expected output signal voltage range?

If you use a high order low pass filter (fc is below 5Hz) .. What is wrong with that?
Give specifications.

Klaus
 

Hello Klaus,

My target is to convert duty cycle to analog value. Input is 5V PWM with varying frequency (and duty), output should be linearly proportional to duty, in the range 0-5V

Using a 5Hz-below RC filter is ok, but with higher frequencies, delay will be higher than acceptable.

Thanks!
 

Hi,

.. this is why I asked for specifications. This means values with units.

* "higher frequencies" ... I don´t know what you think that "higher frequencies are"
* "delay will be higher than acceptable" ... I don´t know which "delay time" is acceptable for you.

***
Why do you think with "higher frequencies" the delay time will be higher?
--> With higher PWM frequency the delay is the same.
--> With higher cutoff frequency the delay will be shorter.

***
For a solution similar to LTC2644..
You need to decide which edge you want to sync
Then use a microcontroller with "capture" feature to get the timestamps of the edges.

Example with sync on rising edge:
Measure the time from one rising edge to the falling edge: = high_time
Measure the time from one rising edge to the next rising edge: = cycle_time

Calculate: duty_cycle = high_time / cycle_time.

Output this value to a DAC.
Alternatively you could generate your own fixed (high) frequency PWM with the calculated duty cycle.
Then use a second order low pass filter on your generated PWM.


Klaus
 

Klaus,

Sorry for the mistake, I intended to write "lower frequencies".

For instance, using a 2.5Hz cutoff frequency RC filter would be OK, but if the source is at 500Hz, change of output will be slow, in hundreds of milliseconds range.

About the MCU alternative, this project will be a full-analog one. So, cannot use a programmable device.
 

Hi,

this project will be a full-analog one.
Click to expand...
Any other informations we should know?

***
Hi,
Analog solution: Sawtooth, 2 x sample_and_hold, analog divider.
* Sawtooth starting with zero after rising edge.
* first SH circuit freezes the sawtooth value with falling edge (SH1)
* divider calculates dc=SH1/Sawtooth
* second S/H freezes divider output (FF style, rising edge triggered) = output.

Klaus
 

Thanks, I will simulate and try this circuitry.

By the way, what about multiplying PWM signal? Does it lead to anywhere?
 

Dividing the signal into a high frequency one I guess. Not sure how to implement, just an analogy to structures like clock dividers.
 

Hi,

With clock divders the duty cycle is not critical (and in many cases it is 50%).

But your target is to measure duty cycle. So most probably you kill exactely the information you are interested in.

Klaus
 

Are switched capacitor filters compatible for this application? I was wondering if I could generate a clock from PWM signal, divide it and feed the clock input of filter.
 

For instance, using a 2.5Hz cutoff frequency RC filter would be OK, but if the source is at 500Hz, change of output will be slow, in hundreds of milliseconds range.
Click to expand...

Not slower than for 5 Hz slow. I guess you want adaptive filtering, unfortunately you never told your specifications clearly.
Surprisingly you didn't yet address output ripple, which is the other relevant specification when designing a low pass filter for the application. If a low pass filter can serve the purpose, it would be a second or third order filter, e.g. of the butterworth type.

If you want adaptive filtering, a circuit with sample and hold seems reasonable, you need to take care that it preserves the signal average.

PLL clocked SC-filter can be another option to make an adaptive filter.

I would appreciate a specification in terms of tolerated ripple and settling time.
 

FvM,

Thanks for your reply and interest. That is correct, I want adaptive filtering.
About the output ripple, it must be less than 5% of output voltage (0-5V)
Settling time should be less than 5ms in any PWM input.

I will try Sample Hold circuitry, but if a simpler circuit exists, that will be life-saving :)
 

Settling time should be less than 5ms in any PWM input.
Click to expand...
How should this be possible with 5 or 50 Hz pwm frequency? An optimal processing scheme would need minimum 1 pwm period to measure the duty cycle. Any analog circuit utilising filters needs additional filter settling time.

If you expect a constant pwm frequency with variable duty cycle, a possible solution could be to implement a f/v converter for the pwm frequency and use it's output voltage as reference for a time-to-voltage integrator, sample it's output on the negative edge.
 

Ofcourse we have to wait for 1 cycle to end:)
I gave the LTC2644 example, and wanted to imitate behaviour with an analog circuit. If you check its datasheet, input to output waveform will be helpful to understand.
 

To achieve the same behavior in an analog circuit, you need an analog divider. Under the restriction of constant or slowly variable pwm frequency, the above sketched solution can work.
 

FvM,

Thanks for reply. What you mean by 'analog divider'?
 

Analog divider circuit, z = y/x. Usually made with analog multiplier and feed back circuit or implemented using log/antilog transistor circuits.

An example for the latter from National Semiconductor AN 30

mult-div.png

- - - Updated - - -

And using 4-quadrant multiplier IC

divide.png
 

Hi,

this project will be a full-analog one
Click to expand...
I wonder what's the idea behind this restriction. Because it makes the system more complex, non flexible and it makes it difficult to react on input signal failure.

What you mean by 'analog divider'?
Click to expand...
Did you miss that I mentioned "analog divider" in post#6 already?

FvM expalined it already.
It makes the circuit a bit difficult.
Decide what should happen when there is no input signal at all? Specifiy the output behaviour with time and voltage.

What happens when the input frequency is too high or too low?

Klaus
 

Yes, that sample hold and abalog divider makes the circuit a bit difficult. I will try both SH/Divider circuit, and switched capacitor filter alternative.
 

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