How to plot the sampling window of the Flipflop..?

Hey All,

How to plot the sampling window of the Flipflop..?

Is this graph mirror image about y-axis for Setup & Hold Time..? (Please follow the attachment)

What do I need to understand by the Positive & Negative Data to Clk Offset in the Graph...?

Follow the attachments for my concern......

Thanks in advance.......

It's not mirrored. Thís are two graphs in one image. Having almost identical setup and hold margins is rather unrealistic, respectively caused by an unusual clock edge reference.

Consider that both graphs belong to different (adjacent) clock edges. You can however extent the hold graph by one clock period to the right and it passes into the setup curve of the next clock cycles. Means you get a sampling window a little bit smaller than one clock cycle.

Thanks a lot for your Quick reply FvM....

My intention behind opening this question is...

How to find the Setup & Hold time of my designed Flipflop....?

I like to just march the D input edges (must test both)
across the CK edge using the td param of a pulsed voltage
source. With a proper initialization of course. Use the
parametric analysis tool, or .MODIF (if a bare SPICE kind
of setup). Look at the Q waveform family-of-curves.
You will see the output act normally at large setup,
the CK-Q delay slide out, then flip to "wrong answer"
as you violate the setup time. Similarly (but opposite)
at the hold data edge.

Layer a delay measurement on this and you can get
a delay-vs-setup-time plot (although some delay
functions deal poorly with "didn't happen", as the graph
may be showing where there is no data). Criticize the
delay against what your digital timing model says is the
cell delay, or the delay you have been tasked to
achieve; the setup it takes to make the delay (plus
comfort margin) is your answer.

Be sure to use realistic D, CK edge rates as this has
some impact to the answer. Box it with min and max
(fanout+wireload) and process corners.