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    Design of folded cascode amplifier

    Dear reader,

    This is my first post. If I did something wrong, please let me know.

    I am trying to design a folded cascode opamp that will be integrated in a sensor read-out design. I need to use a differential amplifier topology. The implementation will be fabricated, as it is part of my graduation assignment. The software I use is Cadence Virtuoso.

    My problem is such: My simulation results tell me that I can achieve pretty decent open loop gain (about 60x, so 35dB), however, when I close the loop for unity gain the closed loop gain is not as expected. And with that I mean: either a very small output signal, or simply a DC signal when it should be AC. I have already tried a lot, but so far not a single time the closed loop worked.

    I included a picture of my schematic. I suspect that I made a simple and trivial mistake. Or my biasing is incorrect.

    The schematic (closed loop):


    Thank you in advance,

    Joost

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    Re: Design of folded cascode amplifier

    Quote Originally Posted by jrom View Post
    Or my biasing is incorrect.
    Very probably. Run a DC simulation & show us a schematic with backannotated operating point voltages, and a further schematic with backannotated operating regions (from same simulation). This will show you (and us) where the problems are.



    •   Alt20th March 2017, 21:25

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    Re: Design of folded cascode amplifier

    Thank you for your reply. I have some questions.

    What should be my approach in finding the operating points? Sweep the bias (DC) sources and measure the output voltages of each device? The operating point would then be the bias voltage for which the output voltage change is steepest?

    I will try to make the backannotated schematics you ask for. I suspect I will upload them tomorrow.



    •   Alt21st March 2017, 07:58

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    Re: Design of folded cascode amplifier

    Dear Joost,

    I have some questions and recomendations:

    - Why you use the V11 source on M4 and not connect a NMOS transistor between M1 and M7 to keep the symmetry?

    - Think about why you implement the R9 resistor. Maybe you can use a second NMOS transistor to have a higher output impedance 2-transistor current source.

    - Looking at the W/L ratio of your transistors I will expect 800u/4u for the PMOS and 400u/4u for the NMOS in order to have a better DC biasing. There’s any design reason to use that geometry values?

    - The AC simulation gives you information about the gain considering that the signals are not going to change the operation point of the transistors. If you are going to fabricate this chip I seriously recommend you to make both, the DC and the transient simulation. Also, do not forget to do the proper Montecarlo simulation or you will have surprises when you measure the real amp on-chip.

    - The loading impedance of 1MOhm is ok, but, that 1fF capacitor is not a realistic approach. As far as I have seen in different chips, the output capacitance of the pads uses to be in the order of pF.

    - If you are going to implement the layout version of this circuit you will need to create a symbol which includes only the transistors and resistors you want to implement on-chip. Also it is good to base the simulation in sub-structures or symbols.

    [...]

    Greetings.


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    Re: Design of folded cascode amplifier

    The load impedance is 20Kohms (10K+10K to 7.5V)
    and this may be too low for your bias current, with
    that bare current source/sink mirror output.

    Test this possibility by vcvs-buffering the output node
    before the feedback is taken.



    •   Alt21st March 2017, 19:24

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    Re: Design of folded cascode amplifier

    I tried to use DC simulations to find operating points for my devices. However, I think I am doing something wrong.

    I swept the bias sources V3, V4 and V11 and measured at the output of the amplifier. I marked the voltage regions for which the output change is steepest. The used differential input was 10mV (7.51V-7.50V).

    All bias sources were approximately in the correct range. I adjusted each bias source to the middle of the ranges.

    Was this approach correct?



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    Re: Design of folded cascode amplifier

    Dear CMOS-Tangram,

    Thank you for you reply.

    - If I add that NMOS to keep symmetry, will the output of my opamp still be single-ended?

    - I added that resistor to reduce the Vgs of M9 and M6, which seemed to reduce the output offset in transient simulation. However, with the adjusted bias voltages, a resistance of 0 ohm gives better results. I'm not sure why.

    - Good point. The process that is used for fabrication is for education purposes, so designing in it is not done often. Currently there is only one person here that did design some circuits in this process. See used these geometries and advised me to use the same, to ensure working devices.

    - Definitely.

    - Also true. So far I was only trying to get the opamp to work with feedback, before exploring its load or limitations. But indeed, probably in the range of pF.

    - I have not tried any layout design yet.

    Joost

    - - - Updated - - -

    Dear dick_freebird,

    I tried vcvs buffering the output node with a common drain amplifier. I was unfamiliar with this. However, it seems to work. For the first time, unity gain and a gain of 2x seem to work.

    However, the feedback gain is about 20-25% off. So I will need to improve it further. Any thoughts on this? Also, it only works with large (100K) feedback resistors in the loop. Does that mean that even after the vcvs buffer, the load impedance is still considered too low? What can I do to improve on this? Add another common drain stage?

    Many thanks!



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    Re: Design of folded cascode amplifier

    Start with the definition of the application load. This
    should be known (or, you should make something up that
    passes a "smell test" - certainly able to drive its own
    feedback network, whose C and R elements may in turn
    be driven by concerns like closed loop bandwidth and
    stability - input capacitance and feedback resistance
    add feedback poles which turn into forward zeroes, etc.).
    And here you should hang the eventual ESD protection
    and pad / packaging capacitance onto the thing, to see
    that aspect.

    I think a Class AB output stage is what a general purpose
    op amp wants. What you have now is more of an OTA
    (with limited current range). It may be suitable for use
    with C-only loads, and switched-C feedback. But is this
    how you'd use it (or, since it appears to be a science
    project, are you at liberty to adapt the application to
    the design rather than the industrial part design flow,
    where design follows an identified application?)?

    The simple structure, and possibly nonideal biasing,
    may make significant gain error / AVOL shortfall even
    taking the feedback loading out of the picture. Might
    play with simply starving back the master current,
    to push devices more into saturation region, and look
    for the response to that "stimulus". Maybe something
    of this sort will reveal itself.



    •   Alt22nd March 2017, 18:49

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    Re: Design of folded cascode amplifier

    Dear Jrom,

    I reply you quite fast. I hope these reply are clear enough, if not I will edit the text to clarify. Also, if any of this explanations are not ok at all don't hesitate to correct me.
    Thank you in advance.

    Quote Originally Posted by jrom View Post

    - I added that resistor to reduce the Vgs of M9 and M6, which seemed to reduce the output offset in transient simulation. However, with the adjusted bias voltages, a resistance of 0 ohm gives better results. I'm not sure why.
    1- Because of the source connected to V7 and the gate connected to V3, M8 and M2 are generating a fixed Ids current.
    2- On the other hand, M0 and R9 are working like a current source. If M0 operates alone (like with the source connected to ground), the Vgs value will be fully controlled by V11 (Because Vgs would be directly Vgs). The effect of R9 on this source is, when you increase Vg of M0, the raise of the Ids current produces an increase in the voltage difference in R9, increasing the Vs voltage in the source node of M0, and reducing the absolute increment of Vgs. As a resume: As big is R9 smaller is the current that you will generate applying a V7 voltage.
    3- Combining 1 and 2 and applying Kirchhoff to node which the source of M3 is you can see that you are injecting the current produced by 1, and subtracting half of the current produced by 2. The rest of the current will flow as Ids of M3. As bigger is this current bigger is going to be the DC voltage at the output node.

    So, if you reduce R9, you increase 2, you subtract more current from 1 and 3 is smaller as it is also the output DC voltage.


    Quote Originally Posted by jrom View Post

    - If I add that NMOS to keep symmetry, will the output of my opamp still be single-ended?
    If you include this transistor you would have a CMOS differential amplifier, whose inputs would be the gates of M9 and M6, and their differential outputs the drain of M3 and M1 (the differential gain would be the same in magnitude if you keep the symmetry including the suggested transistor).

    The main drawback of this differential output is that you will need to DC bias the M1-drain-node output. And if you are not looking for a differential output it is not necessary to complex the design in this way.

    I think that I didn’t give you a good advice on this…



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    Re: Design of folded cascode amplifier

    Dear dick_freebird,

    The amplifier I am designing here will be used in a sensor read-out circuit. The load will be an ADC that is designed in the same technology. I made some initial design of a flash ADC, as these are simple and robust. I don't need very high specs for the ADC. This means that the output of the amplifier will be hooked up to the input of a comparator. This will have a high input impedance.

    Yes, I have the liberty to decide and design every aspect of the implementation (as long as I make reasonable choices).

    I'm not sure what you mean by 'starving the master current'. Could you give me an explanation or direct me to some?

    Thank you for your reply!

    - - - Updated - - -

    Dear CMOS-Tangram,

    Thanks again for you reply.

    I agree with your explanation.

    Exactly, I have no need for a fully differential amplifier. I need a single-ended output voltage that I can feed to an ADC (which is of course referenced to GND). I think that things will be become complicated if I would try to design around a differential output. However, I did consider it previously, and designed a fully differential topology.

    Do you have any thoughts on how to improve my closed loop gain? I now use feedback resistors of about 50k to 500k, the difference is very little. Still, my output is approximately 15% to 20% too low compared to the expected output. I tried loop gains of 1 to 5. Higer gains, like 10, have a larger offset. Perhaps there is a voltage drop somewhere in the design that affects the final common drain stage? I added an image of my latest design. Note that I already adjusted the biasing (current mirrors), the resistors that control the current are placed externally.




  11. #11
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    Re: Design of folded cascode amplifier

    First, separate offset error from gain (which may include
    loading) error. Different causes, different solutions.

    Getting gain higher requires active device gm come up
    and the parallel value of active and load device impedances
    come up as well. Both of these respond to bias current,
    Rout especially to getting Vgs << Vds. Look at any high-Z
    (you wish...) gain node and see what's defining the node
    impedance. Rout goes up as Vgs goes down and Vgs goes
    down as you throw less bias current.

    Gain errors out the back can manifest as front end offset.
    Tie both inputs to center voltage (7.5V, or whatever your
    -real- voltage of interest may be) and see where currents
    which should be balanced, start to diverge in open loop.
    Follow that and balance things out by size / bias.

    Do not try to ratio devices by drawn W. Ratio by fingers.
    Do not try to ratio devices by drawn L, ever.



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