+ Post New Thread
Results 1 to 3 of 3
  1. #1
    Newbie level 2
    Points: 947, Level: 6

    Join Date
    Jun 2012
    Posts
    2
    Helped
    0 / 0
    Points
    947
    Level
    6

    MIG FIFO Requirement

    Hi, I'm quite newbie in Verilog and FPGAs. I'm trying to access the DDR2 SDRAM on my FPGA board (Opal Kelly XEM6310-LX45). I instantiated RAM controller module which i generated with MIG tool in ISE. Now I'm trying to control the interface. I have read UG388 but there is a point that I'm confusing. Does MIG module have Write, Read and Command FIFOs internally, or do I add these FIFOs to MIG externally?

    •   Alt18th March 2017, 15:35

      advertising

        
       

  2. #2
    Advanced Member level 3
    Points: 6,646, Level: 19
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    955
    Helped
    215 / 215
    Points
    6,646
    Level
    19
    Blog Entries
    1

    Re: MIG FIFO Requirement

    I have never used the DDR2 MIG IP core, but as I understand it from Pg16, ug388.pdf, from the block diagram I see that internally it has command (CMD FIFO *) and data FIFOs (32 bit bi-/uni-drectional).
    Then I have this excerpt...
    FIFOs are used at the User Interface of the command path and datapath to queue up memory requests and to manage the transfer from the user clock domain to the memory controller clock domain.

    As I understand it, it means that FIFOs exist just immediately after the user interface ports inside the MIG core.
    .....yes, I do this for fun!


    1 members found this post helpful.

    •   Alt18th March 2017, 23:38

      advertising

        
       

  3. #3
    Newbie level 2
    Points: 947, Level: 6

    Join Date
    Jun 2012
    Posts
    2
    Helped
    0 / 0
    Points
    947
    Level
    6

    Re: MIG FIFO Requirement

    Thank you dpaul.



--[[ ]]--