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Verification of RTl using testbenches

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kaushikrvs

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Can someone tell me what are the guidelines that should be kept in mind while writing testbenches for rtl?
and How does a self checking testbench help in larger designs?
 

kaushikrvs said:
Can someone tell me what are the guidelines that should be kept in mind while writing testbenches for rtl?
and How does a self checking testbench help in larger designs?
Click to expand...

you are asking us to summarise a big area of EDA called verification. that is not realistic.

self checking testbench helps because the user doesn't have to check waveforms or debug messages, the testbench does it for you. it is really impractical to do anything else.
 

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