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  1. #1
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    VHDL code exercise. Please help!!

    Hi, I'm a engineering student and I would like to know if anyone could help me to solve this exercise. From already thank you very much


    Show synthesizable VHDL code for a register unit that performs
    operations shown below. The unit has a 3-bit mode (md) input, an
    asynchronous reset (rs) input, a 1-bit output control (oc) input, and an
    8-bit bi-directional io bus. The internal register drives the io bus
    when oc is ‘1’ and md is not “111”. Use std_logic.
    md=000: does nothing
    md=001: right shift the register
    md=010: left shift the register
    md=011: up count, binary
    md=100: down count, binary
    md=101: complement register contents
    md=110: swap right and left 4 bits
    md=111: parallel load

    •   Alt13th March 2017, 01:09

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  2. #2
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    Re: VHDL code exercise. Please help!!

    Help you, yes. Do all your work you, no.

    Dude, show at least a LITTLE effort.



    •   Alt13th March 2017, 02:02

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  3. #3
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    Re: VHDL code exercise. Please help!!

    sorry. The file was not uploaded, what I wanted to know is if it's okay

    this is the datapth
    Code:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_signed.all;
    use std.textio.all;
    
    entity datapath is
    port( io : inout std_logic_vector ( 7 downto 0);
    		
    		clock ,md1,md2,md3,reset,ic: in std_logic);
    		
    end entity;
    
    architecture arquitectura of datapath is 
    		
    	
    	--- componente enable 
    	component Ena
    	   port ( entrada :in  std_logic_vector(7 downto 0 );
    		       salida  :out std_logic_vector(7 downto 0 );
    		       cambio  :in  std_logic );
    	end component;
    	
    	for all : Ena   use entity work.enable(arqui);
    	----------------------------------------------------	
    	component Ena1
    	   port ( entrada :in  std_logic_vector(7 downto 0 );
    		       salida  :out std_logic_vector(7 downto 0 );
    		       cambio  :in  std_logic );
    	end component;
    	----------------------------------------------------	
    	
    	for all : Ena1   use entity work.enable1(arqui);
    		
    		
    	signal a0,a1,a2,a3,a4,a5,a6,a7,a8,b,b1  : std_logic_vector (7 downto 0);
    	signal ic1 : std_logic;
    	
    	
    	begin 
    		
    		---------------------------------------------
    		-- el carga selector 
    		selector1 : ena port map (io , a0, ic);
    		--selector2 : ena port map (b1 , io, ic1);
    		---------------------------------------------
    		
    		---------------------------------------------
    		u12 : Entity work.pnot(arqui) port map (ic,ic1);
    		---------------------------------------------
    		
    		
    		----------------------------------------------------------------------------------
    		--el selector de operaciones 
    		asigna : Entity work.mux(arqui) port map (a0,md1,md2,md3 ,b,a2,a3,a4,b,a6,a7,a8);
    		----------------------------------------------------------------------------------
    		
    		
    		----------------------------------------------------------------------------------
    		------envio a sus funciones-------------------------------------------------------
    		u2 : Entity work.desplazar_derecha(arqui) port map (a2,b,clock);
    		u3 : Entity work.desplazar_izquierda(arqui) port map (a3,b,clock);
    		u4 : Entity work.contadores(arqui) port map (a4,clock,md1,md2,md3,b);
    		u6 : Entity work.cambiarLugar(arqui) port map (a6,b,clock);
    		u7 : Entity work.CargaParalela(arqui) port map (a7,clock,ic,b);
    		u8 : Entity work.Complemento(arqui) port map (a8,b,clock);
    		----------------------------------------------------------------------------------
    		
    		
    		----------------------------------------------------------------------------------
    		------envio a sus funciones-------------------------------------------------------
    		u10 : Entity work.todoCero(arqui) port map (b,b1,reset);
    		----------------------------------------------------------------------------------
    		
    		
    
    end architecture;
    
    
    -- component derecha
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;
    use std.textio.all;
    
    entity desplazar_derecha is 
     port ( entrada :in  std_logic_vector(7 downto 0 );
    		  salida  :out std_logic_vector(7 downto 0 );
    		  clk :in std_logic );
    		  
    end entity;
    
    architecture arqui of desplazar_derecha is
    			begin 	
    	
    	process (clk)
    			variable aux : std_logic_vector(7 downto 0);
    			variable valor: std_logic;
    			
    		begin 	
    			
    				valor := entrada(0);
    				aux := valor & entrada(7 downto 1 );
    				salida <= aux;
    			
    	end process;
    end architecture;
    	
    
    
    
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.ALL;
    
    entity Mux is
    port(            entrada : in  std_logic_vector (7 downto 0);
                           x1,x2,x3 : in  std_logic ; --- selector de md 000 , 001 , 010 etc....
    							  
    	 a1,a2,a3,a4,a5,a6,a7,a8 : out std_logic_vector (7 downto 0));
    end entity;
    
    	architecture arqui of Mux is
    		begin 
    			process(entrada, x1,x2,x3)
    		begin 
    				
    				IF ( x1 = '0' and x2 = '0' and x3='0' ) THEN
    						a1  <= entrada;
    				END IF;
    				
    				IF ( x1 = '0' and x2 = '0' and x3='1' ) THEN
    						a2  <= entrada;
    				END IF;
    				
    				IF ( x1 = '0' and x2 = '1' and x3='0' ) THEN
    						a3  <= entrada;
    				END IF;
    				
    				IF ( x1 = '0' and x2 = '1' and x3='1' ) THEN
    						a4  <= entrada;
    				END IF;
    				
    				IF ( x1 = '1' and x2 = '0' and x3='0' ) THEN
    						a5  <= entrada;
    				END IF;
    				
    				IF ( x1 = '1' and x2 = '0' and x3='1' ) THEN
    						a6  <= entrada;
    				END IF;
    				
    				IF ( x1 = '1' and x2 = '1' and x3='0' ) THEN
    						a7  <= entrada;
    				END IF;
    				
    				IF ( x1 = '1' and x2 = '1' and x3 = '1' ) THEN
    						a8  <= entrada;
    				END IF;
    			
    --case A is
    --when "000" => a1  <= entrada;
    --when "001" => a2  <= entrada;
    --when "010" => a3  <=entrada ;
    --when "011" => a4  <= entrada;
    --when "100" => a5  <= entrada;
    --when "101" => a6  <=entrada ;
    --when "110" => a7  <= entrada;
    --when "111" => a8  <= entrada;
    
    --when others =>a1 <= '0';
    
    --end case;
    end process;
    end architecture;
    
    
    
    --- contador ascendente y descendente
    
    
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;
    use std.textio.all;
    
    entity contadores is 
     port (  entrada : in std_logic_vector(7 downto 0 );
    			clk 	  : IN std_logic;
    			x1,x2,x3	:in  std_logic;
    		   salida  :out std_logic_vector(7 downto 0 ));
    		  
    end entity;
    
    ARCHITECTURE arqui OF contadores IS
    	
    		BEGIN
    			PROCESS (clk)
    		 variable cont_aux1,cont_aux2 : std_logic_vector (7 DOWNTO 0);
    		
    		BEGIN
    			 cont_aux1 :=  "00000000" ;
    		    cont_aux2 :=  "11111111" ;
    			IF (clk = '1' AND clk'EVENT) THEN
    				
    				IF ( x1 = '1' and x2= '0' and x3 = '0' ) THEN
    			cont_aux1 := cont_aux1 + 1 ;
    			salida <= cont_aux1;
    				END IF;
    				
    				IF ( x1 = '1' and x2= '0' and x3= '1' ) THEN
    			cont_aux2 := cont_aux2 - 1;
    			salida <= cont_aux2;
    				END IF;
    				
    			END IF;
    	END PROCESS;
    
    END ARCHITECTURE ;
    
    
    
    -- component desplazar_izquierda
    
    
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;
    use std.textio.all;
    
    entity desplazar_izquierda is 
     port ( entrada :in  std_logic_vector(7 downto 0 );
    		  salida  :out std_logic_vector(7 downto 0 );
    		  clk     :in std_logic ); 
    end entity;
    
    architecture arqui of desplazar_izquierda is
    			begin 	
    		
    	process (clk)
    			variable aux : std_logic_vector(7 downto 0);
    			variable mover,valor: std_logic;
    			
    		begin 	
    			
    				valor := entrada(7);
    				aux :=  entrada(6 downto 0 ) & valor ;
    				salida <= aux;
    			
    	end process;
    end architecture;



    •   Alt13th March 2017, 02:11

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  4. #4
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    Re: VHDL code exercise. Please help!!

    A few comments: At first glance (I'm too lazy to read the whole thing) ) my impression is that you've made this unnecessarily complicated with multiple components and architectures. Do a search on "VHDL counter" and you'll find much simpler code.

    Std_logic_unsigned is outdated and not a "standard" library. You should use numeric_std instead.

    - - - Updated - - -

    One more thing. To determine whether it's working, you should simulate it! You can a learn a lot about how this all works from your simulation errors.


    1 members found this post helpful.

  5. #5
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    Re: VHDL code exercise. Please help!!

    I find the use of variables unnecessary in this code. The assignments to valor and aux are just wasting time and memory (for simulation).

    I don't get your multiplexer it is not multiplexing anything, what it is doing is demultiplexing (a decoder) entrada into one of eight different a# outputs.



    •   Alt13th March 2017, 16:06

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  6. #6
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    Re: VHDL code exercise. Please help!!

    On the entity of the Counters (entity "contadores") you have this:
    x1,x2,x3 :in std_logic;
    Which I believe is referred to the 3 bits mode inputs (md). To simplify the code, you can create this--> md: in std_logic_vector (2 downto 0); and then instead of doing like this:
    IF ( x1 = '1' and x2= '0' and x3 = '0' ) THEN
    You would do this: if md="100" then ... which I believe is easier and fancier.

    And I do not understand why you have those counters like that because you are using an 8 bit counter to simply sum "1" to it...so you want to have binary counter but instead you have 8 bit counter... useless in my opinion.

    In fact, all the counter is useless. Those auxiliary variables of the counter can be erased all of them and simply say:
    if md="100" then
    salida <= "00000001"; -- or whatever

    if md="101" then
    ...

    - - - Updated - - -

    And furthermore, they will give you a LATCH warning, which is not good.
    Last edited by CataM; 13th March 2017 at 16:29.



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