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Verilog-D for analog Integrator

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ashrafsazid

ashrafsazid

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Hi, It is possible to write a functional verilog-D model for analog Integrator? If possible can you please give me an example?
 

It is possible.

It is very easy to implement integration of even time step.

Implement as Trapesoidal Integration or Simpson Integration.
Here yoy have to generate time event required for time step of integration.
 
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Can you provide me an example? Is it also possible to get the output as voltage?
 

ashrafsazid said:
Is it also possible to get the output as voltage?
Click to expand...
No.
Can you uderstand Verilog-D surely ?

Can you understand https://www.edaboard.com/threads/365005/#2

Available data types are "wire", "reg", "real", "integer".
And you can not use "real" and "integer" as ports.

Simulator for Verilog-D is classified as Signal Flow Simulator.

On the other hand, SPICE Type simulator is classified as Energy Conservative System Simulator, where two physical objects, potential and flow are contrainted.
 
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