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  1. #1
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    module instantiation

    Hello,I have written code for s27 benchmark circuit and counter,I have given output of counter to s27 circuit.When I run the view RTL schematic its showing following error:
    ERROR:Xst:528 - Multi-source in Unit <s27test2> on signal <out<3>>; this signal is connected to multiple drivers.
    Drivers are:
    Primary input port <G3>
    Output signal of FDR instance <str1/d_3>
    how to resolve this?

    I have used instantiation.Below is the code

    Code:
    module s27test2(G1,G2,G3,G0,clock,reset,out,G17);
    input clock,reset,G1,G2,G3,G0;
    output [3:0]out;
    output G17;
    counter str1 (.clk(clock),.rst(reset),.d(out));
    assign G0=out[0];
    assign G1=out[1];
    assign G2=out[2];
    assign G3=out[3];
    s27 str2(.CK(clock),.g0(G0),.g1(G1),.g2(G2),.g3(G3),.g17(G17));
    endmodule

    •   Alt8th March 2017, 06:05

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  2. #2
    FvM
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    Re: module instantiation

    The problem is in the useless assignments to inputs G0..G3. They can be either input ports or driven by str1 d output. Reconsider!



    •   Alt8th March 2017, 06:17

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  3. #3
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    Re: module instantiation

    Yes,I tried that,I want show the inputs G0..G3 in RTL schematic how to do that?
    s27block.jpg



    •   Alt8th March 2017, 07:45

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  4. #4
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    Re: module instantiation

    I want show the inputs G0..G3 in RTL schematic
    Why not, but that's not related to the problem in post #1. Problem is that G0..G3 can't be inputs of module s27test because they are driven by counter str1.



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    Re: module instantiation

    Quote Originally Posted by ecasha View Post
    Yes,I tried that,I want show the inputs G0..G3 in RTL schematic how to do that?
    May be you should tell us what you need to do, instead of asking about broken code where it is impossible to tell what you wanted to do. (Lack of comments in your code doesn't help).

    16 years later and students are still being taught to use antiquated module port definitions when Verilog 2001 allowed the use of C style port definitions (removes the redundant declarations of port names and then their types).



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