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    Dual Clock Synchronization based Verilog Code

    Hi everyone,

    I am designing an analog system which requires a Verilog code that performs the following.

    Inputs : clk1 (30Mhz) , clk2 (250Khz), reset ( So , the clk1 will complete 120cycles in the time clk2 completes one cycle)

    Output : delay[7:0]

    Problem : The output delay[7:0] should increment only if there is a posedge in both clk1 and clk2.

    Clearer words : it should have a functionality like : always @ ( posedge clk1 && posedge clk2)

    All suggestions welcome. (I'm also paralelly working on it :D)

  2. #2
    FvM
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    Re: Dual Clock Synchronization based Verilog Code

    it should have a functionality like : always @ ( posedge clk1 && posedge clk2)
    Not implementable in hardware. If clk2 is already synchronized with clk1 and has a pulse duration of one clock period, it can be possibly used as clock enable signal. Otherwise a toggle synchronizer is the best solution

    Code Verilog - [expand]
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    reg t, t1, t2;
    always @ (posedge clk2) begin
        t <= !t;
    end
     
    always @ (posedge clk1) begin
        t1 <= t; // Specify false path for this transfer
        t2 <= t1
        if (t1^t2)
        begin
          ....
        end
    end


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    •   Alt8th March 2017, 05:49

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  3. #3
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    Re: Dual Clock Synchronization based Verilog Code

    Synthesizable model is not required here. I am going to dump it in an FPGA and use it for the project.
    With respect to your
    I have one solution in mind. Please comment on it.

    Attachment 136750
    Last edited by ads-ee; 8th March 2017 at 18:55. Reason: Fixed picture attachment



    •   Alt8th March 2017, 06:00

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    FvM
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    Re: Dual Clock Synchronization based Verilog Code

    Synthesizable model is not required here. I am going to dump it in an FPGA.
    That's what people call a contradiction in terms. "Dump in FPGA" means synthesis.

    - - - Updated - - -

    Can't read the attachment, the preview picture suggests unrelated (asynchronous) clocks. Thus a proper synchronization is required to achieve predictable behavior without metastable events. A latch won't do.



    •   Alt8th March 2017, 06:26

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  5. #5
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    Re: Dual Clock Synchronization based Verilog Code

    I agree with FvM a latch will likely cause the circuit to fail due to metastable events. It almost seems like you are trying to create a phase detector between two clocks with a large difference in frequencies. Whatever circuit you design to detect (align) the rising edges will likely cause your analog circuit (PLL?) to wander up and down in frequency a lot due to the poor resolution you will end up with. It will almost be required that you hand place the logic so there won't be any surprises when re-implementing the FPGA.

    Maybe you can divide down the 30 MHz (and maybe even the 250KHz) to either 250 KHz or both to 125 KHz (to balance the FF Tco delays), then you can use a simple XOR detector as long as you place the FFs near the last XOR LUT that was placed near the I/O. Doing this divide will require that you start the divide down counters aligned, otherwise you'll likely end up never achieving lock (assuming this is supposed to be part of a phase detector ).



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    Re: Dual Clock Synchronization based Verilog Code

    Quote Originally Posted by Aravind_Selvaraj View Post
    Synthesizable model is not required here. I am going to dump it in an FPGA and use it for the project.
    With respect to your
    I have one solution in mind. Please comment on it.

    Oh boy. I don't know where to begin.



    •   Alt8th March 2017, 16:50

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    Re: Dual Clock Synchronization based Verilog Code

    There is an up counter whose clock is clk1(30Mhz). Since we already know that 120*30Mhz = 4uS or 250Khz(clk2). The output of the counter wcould be in phase with the actual clk2(signal).
    Could you suggest a method which triggers the output when either of clk2(250Khz) or counter output (again 250Khz) hits it first. Could this provide a more precise solution?



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    Re: Dual Clock Synchronization based Verilog Code

    The output delay[7:0] should increment only if there is a posedge in both clk1 and clk2.
    a method which triggers the output when either of clk2(250Khz) or counter output (again 250Khz) hits it first.
    We got two contradicting descriptions, both or unfortunately unclear.



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    Re: Dual Clock Synchronization based Verilog Code

    Sorry for my language. The actual requirement is a trigger signal output which gives out a pulse whenever the posedges of the 2 clocks are very close (i.e. the both the edges occur in a time less than the duration of one period the higher clk (30Mhz)



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    Re: Dual Clock Synchronization based Verilog Code

    Can be build using the previously suggested toggle synchronizer. Because clk2 is delayed in the synchronizer, the divided clk1 has to delayed respectively. Increase the acceptance interval to two clock periods to get +/- 33 ns tolerance between clock edges.


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