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    PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    Hi,

    I am using altera IP core PLL with the setup shown in the image.
    pll_config.jpg


    When I check the waveform in the scope, I have got a sine wave of 2 vpp with a DC component of 1.5 v. The issue here is that am using that clock to sync with the Audio codec WM8731 for I2S communication but it seems that the codec is not understanding that clock waveform. Not sure if this is the right way to send the BCLK to the codec or definitively I need an external circuit. I checked the I2C commands to activate the digital audio interface and all commands have been acknowledge correctly and checked through the scope. Please let me know your thoughts.

    •   Alt3rd March 2017, 21:41

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    FvM
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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    The FPGA has only digital outputs and doesn't output sine waves on it's own.

    I presume the probed output is 3.3V LVCMOS or similar and can be expected to output a full level square wave.

    Most popular fault is to use inappropriate oscilloscope probe or bandwidth limit on the oscilloscope.



    •   Alt4th March 2017, 10:10

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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    @FvM, My scope has a BW 100Mhz, not sure if a frequency of 18Mhz is not able to handle it. However, the way I am measuring the signal is not directly to the pin of the codec but assigning the pins to GPIOs of the FPGA like this:

    Code:
    GPIO_0(10) <= AUD_ADCLRCK;
    GPIO_0(0) <= AUD_BCLK;
    GPIO_0(1)<=s_I2C_SDIN;
    GPIO_0(2) <= AUD_ADCDAT;
    Thanks



    •   Alt8th March 2017, 17:10

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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    Are you sure the board has nothing on those pins already? If there is something driving that pin then you will have contention when driving your output clock and you might very well see what you've seen on your scope.

    You need to look at the schematic of the board and check the GPIO pins you have defined in the SDC to see if they match with the schematic. You might also want to verify there isn't something else on the GPIO pins like switches that toggle between VCC or GND only. Driving shorted outputs on the board is going to damage the FPGA output drivers.

    A 100 MHz BW scope measuring an 18 MHz clock should have no issues.
    If you have a 100 MHz BW scope that can't measure an 18 MHz clock then your scope is garbage and you should get a better one.



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