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    PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    Hi,

    I am using altera IP core PLL with the setup shown in the image.
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    When I check the waveform in the scope, I have got a sine wave of 2 vpp with a DC component of 1.5 v. The issue here is that am using that clock to sync with the Audio codec WM8731 for I2S communication but it seems that the codec is not understanding that clock waveform. Not sure if this is the right way to send the BCLK to the codec or definitively I need an external circuit. I checked the I2C commands to activate the digital audio interface and all commands have been acknowledge correctly and checked through the scope. Please let me know your thoughts.

    •   Alt3rd March 2017, 22:41

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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    The FPGA has only digital outputs and doesn't output sine waves on it's own.

    I presume the probed output is 3.3V LVCMOS or similar and can be expected to output a full level square wave.

    Most popular fault is to use inappropriate oscilloscope probe or bandwidth limit on the oscilloscope.



    •   Alt4th March 2017, 11:10

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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    @FvM, My scope has a BW 100Mhz, not sure if a frequency of 18Mhz is not able to handle it. However, the way I am measuring the signal is not directly to the pin of the codec but assigning the pins to GPIOs of the FPGA like this:

    Code:
    GPIO_0(10) <= AUD_ADCLRCK;
    GPIO_0(0) <= AUD_BCLK;
    GPIO_0(1)<=s_I2C_SDIN;
    GPIO_0(2) <= AUD_ADCDAT;
    Thanks



    •   Alt8th March 2017, 18:10

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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    Are you sure the board has nothing on those pins already? If there is something driving that pin then you will have contention when driving your output clock and you might very well see what you've seen on your scope.

    You need to look at the schematic of the board and check the GPIO pins you have defined in the SDC to see if they match with the schematic. You might also want to verify there isn't something else on the GPIO pins like switches that toggle between VCC or GND only. Driving shorted outputs on the board is going to damage the FPGA output drivers.

    A 100 MHz BW scope measuring an 18 MHz clock should have no issues.
    If you have a 100 MHz BW scope that can't measure an 18 MHz clock then your scope is garbage and you should get a better one.



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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    Unfortunately that's the only oscilloscope I have right now. I checked the GPIO schematics and I am getting the signals and grounds properly connected. The only thing I noticed is that it says VCC instead VDD which according FvM comment, not sure if they made a label mistake or definitively the GPIOs are not LVCMOS. Anyways, I went ahead and decided to send that signal to the codec and am getting the analog audio to the digital stream as it should so the codec understands the that wave form, whatever it is.



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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    Maybe you scope or probe is broken.

    Does your scope have a 1MHz probe calibration output on it? see if you get a decent square wave trace using that. If not...see the first sentence.

    In regards to your Vdd and Vcc confusion: https://en.wikipedia.org/wiki/IC_power-supply_pin they are the same thing the positive supply voltage.



    •   Alt10th April 2017, 18:47

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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    Most common problem is failure to remove ground clip and long wires in breadboard. Only use 10:1 probe with clip and gnd wire removed and use proper <1cm spring probe barrel and probe pin ONLY.

    Problem is LPF effect of probe capacitance (not tip) of 60-70pf/m and 100-150nH/cm ground or signal wire <1mm with high Q resonance RLC in 25 to 500MHz band depending geometry of paths. I only use 50 Ohm terminations above 20MHz with series pad match or better design for textbook waveforms. or ignore the natural ringing without.

    Above 200MHz special short pin active diff probes or SMA to 50 Ohm coax and 50 Ohm load with 2:1 attenutatuon from 50 ohm 5V Cmos or 25 ohm ALVC CMOS
    Last edited by SunnySkyguy; 10th April 2017 at 18:58.
    A good design question lists your overall requirements™ The best question deserves a better answer. ™
    ... Tony Stewart EE since 1975



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    Re: PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    @ads-ee, I did test the probes first thing when I faced the issue and were working, perfect square wave form at 1M.

    @SunnySkyguy, It is a good tip to consider transmission line effects but in my case did not see any difference.

    I am currently using a development and educational board and I have not check the signal at the codec IC pin itself. Knowing that the system is working I will move on designing the dual clock RAM. Thanks



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