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Is everything okay with my synthesis report

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hcu

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Hello,

I ran synthesis on a IP many times with a variation in the frequency each time. and no additional constraints given during synthesis to the design.

please look into the attachment , i observed a consistent zero slack from 500 Mhz to 1 Ghz. Is everything ok or iam missing anything ? give some suggestions

Screenshot-1.png
 

hcu said:
Hello,

I ran synthesis on a IP many times with a variation in the frequency each time. and no additional constraints given during synthesis to the design.

please look into the attachment , i observed a consistent zero slack from 500 Mhz to 1 Ghz. Is everything ok or iam missing anything ? give some suggestions

View attachment 136548
Click to expand...

It is possible everything is ok. You can check the design area, it should be increasing as more and more buffers and large cells are put in your design.
 

yes , area is increased from 318k um2(@100 Mhz) to 324k um2(@1G). so, any thumb rule to say the maximum frequency for this design.
what i am thinking is, at 100 Mhz i.e 10000ps i got a slack of 7000 ps. so 10000 - 7000 = 3000 ps which is around ~ 300 Mhz.
so if i keep my f =300 mhz i should get a 0 slack for sure approx. but as per sheet , it is going upto 1 G.
 

hcu said:
yes , area is increased from 318k um2(@100 Mhz) to 324k um2(@1G). so, any thumb rule to say the maximum frequency for this design.
what i am thinking is, at 100 Mhz i.e 10000ps i got a slack of 7000 ps. so 10000 - 7000 = 3000 ps which is around ~ 300 Mhz.
so if i keep my f =300 mhz i should get a 0 slack for sure approx. but as per sheet , it is going upto 1 G.
Click to expand...

it is not that simple. the synthesis tool will use more and more advanced tricks once you start to request challenging constraints.

one way to find the maximum, or very close to maximum, is to largely overconstrain the design.
 

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