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what is the ideal bus capacitance for an i2c and a spi bus?

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kaushikrvs

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what happens if I use high frequency signals and go past the cut off frequency ?
 

Hi,

* ideal capacitance: 0pF
* how do you define cutoff frequency in this (both) regard?

Klaus
 

I2C speed is actually limited by the bus capacitance, although "cut-off frequency" isn't the usual term.You find respective calculations in the I2C specification by Philips/NXP. Due to the fact that the specification has fixed speed limits of 100/400 kHz, bus capacitance isn't a problem for usual applications.

SPI can be implemented with impedance matched transmission lines and doesn't suffer from cable capacitance in this case.
 

If we increase the capacitance of the bus then the data rate decreases and that's the reason the datarate of i2c is limited to 3.4 mbps.
 

Hi,

I'd say this high speed I2C is a very special mode.
You need
* a high speed master
* a high speed slave
* special wiring / PCB layout

Do you know a true "high speed master"? (I don't)
Do you know a true "high speed slave"? (I don't)
Do you know a usefull application where a high speed I2C has a benefit over SPI? (I don't)

For sure "capacitance" is one limit, but there are many other problems that prevent me from using a "high speed I2C" bus.

Don't get me wrong. I often use I2C. I use it for low data rate transfer because it's ease of use. But I don't find the high speed usefull.

In one system we used SPI over LVDS via a backplane in a 19" rack system. It's easy to transfer 5MBytes/s simultaneously in both directions. Impossible with I2C.
(For communication on one PCB one doesn't need LVDS.)

Klaus
 

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