Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[Moved]: Compensation in frequency locked loop

Status
Not open for further replies.
D

deba_fire

Full Member level 3
Joined
Jul 3, 2007
Messages
151
Helped
14
Reputation
28
Reaction score
15
Trophy points
1,298
Activity points
2,383
Hi All,

In the attached frequency locked loop, why is there a need of compensation network formed by Rz,Cz, and Cc? As far as I see there is only one integrator in the closed loop, the OTA. The oscillator from vctrl to output frequency is just a gain block since the output variable of interest is just frequency. Single integrator loops are inherently stable, so why is there a need of compensation?

Is there some small signal modelling which I am missing?

Thanks
 

Attachments

  • fll.png
    fll.png
    36.8 KB · Views: 114

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top