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RC extraction in SoC encounter

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oAwad

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I'm trying to understand the meaning of "relative C threshold" and "total C threshold" when I select timing->Analysis condition->specify RC Extraction mode.
ask1.PNG

Does it depend on PDK and if yes, where can I find this info in my PDK ?

Another question, is it possible to generate only the coupling capacitance in the layout ? (nothing in SPEF file except coupling cap.)

Thanks
 

when you set process node using setDesignMode -process , the tool will automatically set the recommended value. you can refer to encounter user guide for the exact meaning。Not sure if you can generate only the coupling capacitance，never tried this before。
 

idanceu said:
when you set process node using setDesignMode -process , the tool will automatically set the recommended value. you can refer to encounter user guide for the exact meaning。Not sure if you can generate only the coupling capacitance，never tried this before。
Click to expand...

I used Nangate Open Cell Library 45nm for my design. When I entered "getDesignMode" I found design mode was set to process 90.

So I have some questions here:

1) So should I have set the design mode to 45nm process before routing ? or it's fine if I specify it just before RC extraction ?
2) How it wasn't automatically set by encounter when I first imported my LEF and netlist files ?
3) When I specified the design mode to 45nm, I got the same coupling capacitance values between the wires (given same conditions)...should the values be different between 45nm extraction and 90nm extraction ? or since given the same conditions (same width, separating distance, common length,...) there will be no change ?


Sorry for my many questions :)
 

oAwad said:
I used Nangate Open Cell Library 45nm for my design. When I entered "getDesignMode" I found design mode was set to process 90.

So I have some questions here:

1) So should I have set the design mode to 45nm process before routing ? or it's fine if I specify it just before RC extraction ?
2) How it wasn't automatically set by encounter when I first imported my LEF and netlist files ?
3) When I specified the design mode to 45nm, I got the same coupling capacitance values between the wires (given same conditions)...should the values be different between 45nm extraction and 90nm extraction ? or since given the same conditions (same width, separating distance, common length,...) there will be no change ?


Sorry for my many questions :)
Click to expand...

1) set it to 45 at the time you start encounter. it affects all sorts of implementation tasks.
2) user has to set, not the tool. tool cannot infer technology node from LEF.
3) depends on what type of extraction you performed. are you using captables or QRC files?
 

ThisIsNotSam said:
1) set it to 45 at the time you start encounter. it affects all sorts of implementation tasks.
2) user has to set, not the tool. tool cannot infer technology node from LEF.
3) depends on what type of extraction you performed. are you using captables or QRC files?
Click to expand...

I'm using captables provided by Nangate corporation so should I apply a scaling factor or as long as the company provides it then I won't have to scale ?

Is there any commands other than "setDesignMode" I have to perform in the P&R process ? (what I do is import LEF & timing -> floorplan -> power rings -> place std cells -> nanoroute -> optimization -> RC extraction -> timing reports -> export GDSII)...anything I'm missing ?
 

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