l.chelini
Newbie level 2
Hi,
I would like to estimate the power consumption of my ASIC design at each clock cycle.
At the moment I have set up the following flow:
1) Generate the netlist using RTL compiler.
2) Dump the VCD file using NC-sim and the netlist obtained at step 1.
3) Back in RTL compiler, for each clock period I want to monitor I annotated the VCD on the netlist and I print out the power information using the command "report power".
Does it make sense ?
Thanks.
I would like to estimate the power consumption of my ASIC design at each clock cycle.
At the moment I have set up the following flow:
1) Generate the netlist using RTL compiler.
2) Dump the VCD file using NC-sim and the netlist obtained at step 1.
3) Back in RTL compiler, for each clock period I want to monitor I annotated the VCD on the netlist and I print out the power information using the command "report power".
Does it make sense ?
Thanks.