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Suggestion required to make gain positive and NF less than7.0dB

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pforpashya

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Hello again,

Well I have designed an mm wave amplifier(this is just first stage), as I intent to add at least two more stages and first stage being NF optimization and matching and second for gain.

Here bias point of the amplifier is 4mA at Vds=1.2 and Vgs1=0.7v and Vgs2=1.0v with width of each transistor is 20um such that we will get Jopt=0.2mA/um

on paper to achieve above parameters we will have to have vgs-vt=0.3v and gm of 25.80mS (W/L)=333.333 L=60nm

Now the MOSFET model used is BSIM4 with all default parameters except Vt0=0.4v(Don't know how this will affect Vt as I don't know how to calculate Vt )
but assuming Vt=0.5 I given vgs of bottom mosfet as 0.7V

Now I am attaching the schematic as well as other result. and plz tell me what can be done to get positive gain and NF below 7dB

ps: impedance matching is not accurate I know but I guess that is not big issue
 

Attachments

  • Amp_1.jpg
    Amp_1.jpg
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  • s11.jpg
    s11.jpg
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  • gain_and_nf.jpg
    gain_and_nf.jpg
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W=20um and L=60nm @ 60Ghz ?? It will never work due to high intrinsic capacitances @ 60GHz.
I guess you did increased too much the W to get the right bias current and you arrived W=20um.. Right ??
Vt is very important parameter for MOS transistor.It's threshold voltage for Vgs and it contributes into Ids directly. Therefore check this parameter from your sources and apply it correctly otherwise you will find 20um/60nm absurd values for 60GHz.
 

MOSFET2 is in near triode region.

Increase Vdd or Vg of MOSFET1.

Vds(MOSFET1)=1.2-0.45=0.75Volts
Vds(MOSFET2)=450-6.39=443.61mVolts
 
Last edited:
W=20um and L=60nm @ 60Ghz ?? It will never work due to high intrinsic capacitances @ 60GHz.
I guess you did increased too much the W to get the right bias current and you arrived W=20um.. Right ??
Vt is very important parameter for MOS transistor.It's threshold voltage for Vgs and it contributes into Ids directly. Therefore check this parameter from your sources and apply it correctly otherwise you will find 20um/60nm absurd values for 60GHz.

As I already said this first stage for keeping noise less and for that I chosen W as 20um.

Ok. can you suggest me the ideal value of W at 60Ghz, is it should be around 2 to 3 um ?I guess then I have to reduce the Ids from 4 mA to some lower value as 1 or 0.5mA.

- - - Updated - - -

MOSFET2 is in near triode region.

Increase Vdd.

Vds(MOSFET1)=1.2-0.45=0.75
Vds(MOSFET2)=0.45-0.013=

yeah thanks. I will increase it to 1.5V and see what happens...
 

pforpashya said:
Now I have changed VDD to 1.5V
but due to this 450mv has become 609mV
Is there any improvement regarding NF and Gain ?

pforpashya said:
MOSFET 1 VG is still 1.0V
so MOSFET 1 Vgs becomes 1-0.609=0.4
as vt0 is 0.4 vt will be greater than 0.4 right?
I think early voltage Va is relative low.
Ids=beta*(1+Vds/Va)*(Vgs-Vt)^2

Show me characteristics of single MOSFET.
 

No.
Single MOSFET Characteristics.
Vds-ID, S21, NF, ft, Gmax, etc.

Your configuration is cascode with diode connected MOSFET.

yeah. thanks for your comment . I will redesign it again. come to know my mistake

can I send you a friend request?

one last question is width of MOSFET is higher i.e. 20um at 60ghz? so that next time I will go with lesser width
 

can I send you a friend request?
No.

one last question is width of MOSFET is higher i.e. 20um at 60ghz?
I don't think so.

http://www.jatit.org/volumes/Vol77No3/7Vol77No3.pdf
http://www-g.eng.cam.ac.uk/mentor/cmos-60G/Design of CMOS for 60GHz applications.pdf

I recommend to connect Vg of MOSFET1 to Vdd.

pforpashya said:
ok. I think I have made mistake in DC analysis
I have to set q bias point for both MOSFET 1 and MOSFET 2 separately right?
No.
You use same MOSFET for MOSFET1 and MOSFET2.

The following might be useful for you.
**broken link removed**
 
Last edited:


Now I have increased VDD to 1.8V

this is VG of MOSFET 1

Voltage between MOSFET 1 and MOSFET 2 is 1.08 so Vgs of MOSFET 1 is 0.72v

which is approx. same as VGs of MOSFET 2

Now drain current has increased to 8.48mA due to all this

how to compensate this current

- - - Updated - - -

Apart from optimization of Bias and MOSFET sizes,
your schematic is very far from practical 60GHz Amplifier.

https://www.keysight.com/upload/cmc_upload/All/Webinar_60-GHz_RDK_Agilent-TSMC_03May2012_final.pdf

Yeah I know, I have to replace lumped elements with transmission lines.......can u give me any link where it is explained in detail how to convert 10pH inductor or100fF capacitor to transmission line
 



Do you think who can understand your situation with your above description ?

Study and consider how to describe sentences.

Sorry my bad

I tried to take VAC source from sources frequency domain and placed it in series with DC VGS. Then I tried to change value of this AC source to AC_vgs=1 but it gives me error

am I doing correctly?
 

I tried to take VAC source from sources frequency domain and placed it in series with DC VGS. Then I tried to change value of this AC source to AC_vgs=1 but it gives me error
am I doing correctly?
Show us ADS Netlist or Schematic.

I recommend you to attend ADS training class held by Keysight technology with paying money.
 

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