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AES encryption with glowing LED after decryption

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Wesley90

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Hello team,

I am a beginner learning to use verilog coding to measure power on Xilinx-FPGA. Custom-built circuit.
IDE-- Xilinx ISE 14.7
I want to check if my AES encryption and decryption design works on an FPGA (with the highest switching activity so as to compare the estimated and measured values). The code below is just the TOP MODULE.

I also want to glow 6 use LEDS. I have few doubts. Kindly help.

1. Will I be able to drive the LEDs on the board (using ucf file) if it is declared as shown below?
2. Can I assign the reg "led" to a port directly in the ucf file?
3. How do I get the highest switching activity/toggle rate for this design (alpha=100)? and how should I change my inputs to achieve this?
I need this alpha=100 value since I am comparing my measured value (using current sensing technique) with the tool estimated value(Xpower analyzer)?
4. How do i use the system clock available? (100Mhz)?


Kindly correct me. I am ready to learn anything new that could help me develop my verilog and tool usage skills.

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module SD_TOP_with_DNA_Coder (clk,led,Plain_Text_Out); //Plain_Text_In,Key,
 
  reg [127:0]Plain_Text_In; 
  reg [23:0]Key;
  output [127:0]Plain_Text_Out;
  output [5:0] led;
  reg [5:0] led;
  wire [127:0]Cipher_Text;
  wire[143:0]DNA_Key;
  input clk;
 
  always@(posedge clk) 
  begin
    Plain_Text_In = 128'd12345;
        Key = 24'd1010;
    #10;
        if (Plain_Text_Out==Plain_Text_In)
            led = "111111";
        else
            led = "000000";
    #100;
        Plain_Text_In = 128'd5678565;
        Key = 24'd11122;
    #10;
        if (Plain_Text_Out==Plain_Text_In)
            led = "111111";
        else
            led = "000000";
    #100;
    end
 
SD_DNA_Code_Block DNA_Coder (
    .Key(Key),
    .DNA_Key(DNA_Key)
    );   
 
   S_Topmodule_AES_Encryption AES_Design (
    .Plain_Test(Plain_Text_In), 
    .Key(DNA_Key[127:0]), 
    .Cipher_Test(Cipher_Text)
    );    
 
   S_AES_Decryption Decryption_Unit (
    .Cipher_Text(Cipher_Text), 
    .Key(DNA_Key[127:0]), 
    .Plain_Text(Plain_Text_Out)
    );
 
endmodule
 
Last edited by a moderator:

you have a bunch of #xx statements in an always block. that is not synthesisable nor will it generate the behaviour you are looking for. you need an FSM.
 

Thank you :) I have removed the # statements. Can you tel me how do I correct this code?
I just need a change in inputs after every clock cycle
 

Similarly you can't expect a meaningful synthesizable AES module without a clock.

Restart with a synthesizable design.
 

Sorry, I am not quite getting a hang of it.
How do i use the system clock here?

- - - Updated - - -

I am unable to figure out how to change the input (PLain_Text_In) at every positive edge of the clock.
Please help me with this part alone

Code: 
always@(posedge clk) 
  begin
    Plain_Text_In = 128'd12345;
        Key = 24'd1010;
    
        if (Plain_Text_Out==Plain_Text_In)
            led = "111111";
        else
            led = "000000";
    
        Plain_Text_In = 128'd5678565;
        Key = 24'd11122;
    
        if (Plain_Text_Out==Plain_Text_In)
            led = "111111";
        else
            led = "000000";
    
end
 
Last edited by a moderator:

start from the basics. where did you get this AES core from? are you sure it can compute the encryption in a single clock cycle?

then go and read about FSMs. you cannot code the intent you want without one.
 

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