synthesizing takes too long time

Code VHDL - [expand]
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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:05:19 02/07/2017 
-- Design Name: 
-- Module Name:    vhdl_data - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity vhdl_data is
 
 
port(
Clk : in std_logic; -- processing clock
we : in std_logic; -- write enable signal
 
data_out : out std_logic_vector(8 downto 0)
); -- output data from memory 
end vhdl_data;
 
architecture Behavioral of vhdl_data is
 
------------------------------------ RAM declaration
type memory1 is array (0 to 1999) of STD_LOGIC_VECTOR (8 DOWNTO 0);
signal  dat2 : memory1 :=(others => "000000000");
 
type memory2 is array (0 to 999) of STD_LOGIC_VECTOR (8 DOWNTO 0);
signal  dat : memory2 :=(others => "000000000");
-------------------------------------- Signal declaration
signal j : integer;
signal kout1 : integer:=1;
 
signal k2 : integer;
begin
 
process(Clk, we)
begin
if (rising_edge (clk)) then
if we = '1' then -- In this process writing the input data into ram
---
dat2 (kout1+conv_integer(dat2(kout1-1))) <= dat (j);
--
dat2 (kout1-1) <= dat2 (kout1-1)+1;
end if;
 
end if;
end process;
 
data_out <= dat2(k2); -- Reading the data from RAM
 
end Behavioral;