Ali_louati
Newbie level 4
Hello guys,
I am thankfull to be part of this forum.
I'm working with a design including just one clock ( benchmark ITC 99 design).
My objectif is to reproduce one of the straggered clock scheme (attached) that I found in this paper (Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains).
My problem that I tried to read the Tessent manual, and I didn't found how to add derived clocks from the refernce clock.
Did any one did something similar to that. Are we able to do those kind of scheme with a design containing just one clock?
I'm using Dft advisor and Fastscan
I am thankfull to be part of this forum.
I'm working with a design including just one clock ( benchmark ITC 99 design).
My objectif is to reproduce one of the straggered clock scheme (attached) that I found in this paper (Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains).
My problem that I tried to read the Tessent manual, and I didn't found how to add derived clocks from the refernce clock.
Did any one did something similar to that. Are we able to do those kind of scheme with a design containing just one clock?
I'm using Dft advisor and Fastscan