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[SOLVED] How to PMI in Vivado

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LatticeSemiconductor

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This is my 1st time using Vivado Design Suite. I need a FIFO. Where can I get the component declarations of Xilinx for parametric module instantiation?

thanks
 

LatticeSemiconductor said:
This is my 1st time using Vivado Design Suite. I need a FIFO. Where can I get the component declarations of Xilinx for parametric module instantiation?

thanks
Click to expand...

What? I'm not sure if you mean you want to know how to instantiate a FIFO or not? It is the same as instantiating any IP core with any vendors tools. If you want the instantiation template produced by the IP core generator for VHDL then look at the .vho file there isn't a file for Verilog.
 

What I ment was a Parameterized Module Instantiation (PMI). It is basically the same thing without using IP core generator. You declare the component, and instantiate it.

- - - Updated - - -

This is an example PMI:

Code VHDL - [expand]
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--!
--! fifo component
--!
component pmi_fifo is
   generic (
      pmi_data_width       : integer := 18;                 -- (2 - 256)
      pmi_data_depth       : integer := 256;                -- 
      pmi_full_flag        : integer := 256;                -- (1 - data_depth)
      pmi_empty_flag       : integer := 0;                  -- 
      pmi_almost_full_flag : integer := 252;                -- (1 - 512)
      pmi_almost_empty_flag: integer := 4;                  -- (1 - 512)
      pmi_regmode          : string := "reg";               -- "reg", "noreg" : enable registered output
      pmi_family           : string := "EC" ;               -- EC, ECP3, XO, XO2
      module_type          : string := "pmi_fifo";          -- 
      pmi_implementation   : string := "LUT"                -- "EBR", "LUT"
   );
   port (
      Data                 : in std_logic_vector(pmi_data_width-1 downto 0);
      Clock                : in std_logic;
      WrEn                 : in std_logic;
      RdEn                 : in std_logic;
      Reset                : in std_logic;
      Q                    : out std_logic_vector(pmi_data_width-1 downto 0);
      Empty                : out std_logic;
      Full                 : out std_logic;
      AlmostEmpty          : out std_logic;
      AlmostFull           : out std_logic
   );
end component pmi_fifo;
 
--!
--!  instanciate EXAMPLE
--!
I0_EXAMPLE : pmi_fifo
generic map (
   pmi_data_width        => 18,
   pmi_data_depth        => 256,
   pmi_full_flag         => 256,
   pmi_almost_full_flag  => 252,
   pmi_almost_empty_flag => 4,
   pmi_regmode           => "reg",          -- "reg", "noreg"
   pmi_family            => "ECP3" , 
   pmi_implementation    => "EBR"           -- "EBR", "LUT"
)
port map (
   Data                  => svEXAMPLEData ,
   Clock                 => sfEXAMPLECLK ,
   WrEn                  => sfEXAMPLEWrEn ,
   RdEn                  => sfEXAMPLERdEn ,
   Reset                 => sfEXAMPLERST ,
   Q                     => svEXAMPLEQ ,
   Empty                 => sfEXAMPLEE ,
   Full                  => sfEXAMPLEF ,
   AlmostEmpty           => sfEXAMPLEAE ,
   AlmostFull            => sfEXAMPLEAF 
);
 
signal svEXAMPLEData: std_logic_vector (18-1 downto 0); --! EXAMPLE input data
signal sfEXAMPLECLK : std_logic;                       --! EXAMPLE Clock
signal sfEXAMPLEWrEn: std_logic;                       --! EXAMPLE write enable
signal sfEXAMPLERdEn: std_logic;                       --! EXAMPLE read enable
signal sfEXAMPLERST : std_logic;                       --! EXAMPLE assynchronous reset, active high
signal svEXAMPLEQ   : std_logic_vector (18-1 downto 0);  --! EXAMPLE output data
signal sfEXAMPLEE   : std_logic;                       --! EXAMPLE empty flag
signal sfEXAMPLEF   : std_logic;                       --! EXAMPLE full flag
signal sfEXAMPLEAE  : std_logic;                       --! EXAMPLE almost empty flag
signal sfEXAMPLEAF  : std_logic;                       --! EXAMPLE almost full flag
 

Are you looking for something like the FIFO_DUALCLOCK_MACRO in the unimacros library in the 7 Series FPGA and Zynq-7000 AP SoC Libraries Guide for HDL Designs? I've never used it so I don't know much about it beyond that there are instantiation templates for both VHDL and Verilog examples in the document.

I'm not really getting why it is a problem to use the core generator tool to make a FIFO with the options you want or to run a tcl script that generates a FIFO core. If you want a non-Xilinx IP FIFO core then you'll have to write your own, like I did for cross platform development across multiple FPGA vendors. (before you ask, I can't post it).
 
From what I recall, there were three levels. You could use FIFO36 and similar, FIFO_DUALCLOCK_MACRO, and then coregen. I think some coregen's actually did have a wrapper around a very detailed core.

I seem to recall the macro having some issues in the first release and also not offering much over FIFO36. The issue is that you still don't have a generic fifo -- it can't go above 36kbit.

Coregen is ok, but it is a bit clunky depending on your design flow. For example, it could mean opening a VNC session to get the Vivado GUI, opening the coregen, generating the core with fixed parameters. waiting for it to generate (years ago this actually took a minute or two). Then simulating/testing and realizing the depth was wrong because the GUI was buggy and changed depth if you changed width... (I'm not sure if this has ever been fixed. It was a bug for at least five years.)

After all that, you get a fixed sized core. If you want to have generics for size/depth, you have to create multiple versions and then keep them up to date. edk actually had a system for that, as their IP cores were configurable and used fifo/bram cores.

Also, there was the awesome corner cases if you gave the core a generic name like "eth_rx_fifo" and then resized it only to have coregen silently fail to write the output due to insufficient permissions. The old core would gladly be used.


--edit: I just remembered the issue with the first release. The VHDL version used unconstrained ports and didn't take care of the common pitfalls -- can't have "open" for unconstrained outputs, assuming "0" exists as an index, and assuming a "downto" direction.
 
ads-ee said:
Are you looking for the unimacros library?
I'm not really getting why it is a problem to use the core generator tool to make a FIFO with the options you want or to run a tcl script that generates a FIFO core.
Click to expand...


exactly what i was looking for, thanks :thumbsup:. I use these PMI (or unimacros) quite frequently. I have them as code snippets and they appear 'as i type'. It takes me no less then 3 seconds to declare and instantiate them and they are parameterizable. No need to maintain it or keep several versions in your project. With the coregen you need to wait for it to launch, and crawl through the taps for configuration.

Although I have to admit, the Xilinx tools are a lot more responsive so there isn't really any 'launching'. I noticed these unimacros are a lot more limited than the PMI .

Also, the core generator has more options available than PMI (like watermark thresholds). As for the buggy GUI I only noticed this once with Lattice Diamond.

vGoodtimes said:
Then simulating/testing and realizing the depth was wrong
Click to expand...
-> this also happens easily with invalid generics on your PMI.
 

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