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Input Buffer design (detailed)

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sys_eng

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I have some questions regareding to this detailed input buffer design.

1) CKE_input_buffer.jpg

1)on differential input, there's a CPAR3=3F capacitance. How do you implement this capacitance?

2)waht's the purpose of M1 to M6?
 

CPAR probably denotes parasitic capacitance from the
layout, hand-annotated to the schematic for simulation
realism. It's implemented by the act of wiring stuff up.

M1-M6 look like MOS capacitors, to slow down that
inverter's output edges (usually done to add a crude
delay, although the purpose of -that- is not clear
offhand).
 

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