andrea_mori
Member level 2
I'm new to FPGA design, so I need some tips to start a digital audio project.
I'm planning to build a discrete ladder digital to analog converter with the following features:
- I2S input 16/24/32 bit 44.1/88.2/176.4/48/96/192 kHz sample rate (maybe also 352.8/384 KHz)
- 24 bit ladder network (last 8 bit discarded) at the above sample rate
- ladder network: 6 bit thermometer + 18 bit R2R
- sign magnitude notation
- voltage output
- ladder fed by parallel data: 2 x 23 mosfet switches + sign
- latch with several OCTAL D-TYPE FLIP-FLOPS
- mosfet switches and ladder isolated from the logic using digital isolator
- 2 external master clocks at 22.5792/24.576 MHz (or 45/49 or 90/98 MHz, depending on the speed required from the FPGA to do its job)
The FPGA should:
- receive I2S (BCK, WS and DATA)
- detect the sample rate
- detect the bit depth
- store data in a FIFO (SRAM at least 4Mb)
- select the right sample rate family (44.1x or 48x) to choose the right external oscillator
- read data from the FIFO
- add some bits if required (input 16/24 bit)
- convert the notation from 2's complements to sign magnitude
- decode the thermometer MSB, 6 to 64
- provide the sign to the digital isolator
- output parallel data, 81 I/O per channel (162 I/O total)
I have some questions for FPGA experts:
- I assume to use the I2S clock (BCK max: 12.288 MHz for 192kHz/32 bit or 24.576 MHz for 384kHz/32) for FPGA timing to manage I2S receiver and store data in the FIFO. Is that correct?
- Then I assume that the FPGA should run at higher clock to manage the other process. Correct?
- So I have different clock domains inside the FPGA. How can I select the right speed clock to do the other processes?
- The latch clock for the DAC is the most crucial signal to generate. Do you think is it better to generate the latch clock from the FPGA or externally dividing the master clock oscillators (for example using something like a 74AC161 counter)?
- What FPGA do you suggest?
- What mux device to switch between the 2 master clock?
I cannot solder BGA, so to build a prototype I need an FPGA development board. Is there any FPGA dev board with such this I/O (around 200)?
Any tips will be very appreciated.
Thanks
I'm planning to build a discrete ladder digital to analog converter with the following features:
- I2S input 16/24/32 bit 44.1/88.2/176.4/48/96/192 kHz sample rate (maybe also 352.8/384 KHz)
- 24 bit ladder network (last 8 bit discarded) at the above sample rate
- ladder network: 6 bit thermometer + 18 bit R2R
- sign magnitude notation
- voltage output
- ladder fed by parallel data: 2 x 23 mosfet switches + sign
- latch with several OCTAL D-TYPE FLIP-FLOPS
- mosfet switches and ladder isolated from the logic using digital isolator
- 2 external master clocks at 22.5792/24.576 MHz (or 45/49 or 90/98 MHz, depending on the speed required from the FPGA to do its job)
The FPGA should:
- receive I2S (BCK, WS and DATA)
- detect the sample rate
- detect the bit depth
- store data in a FIFO (SRAM at least 4Mb)
- select the right sample rate family (44.1x or 48x) to choose the right external oscillator
- read data from the FIFO
- add some bits if required (input 16/24 bit)
- convert the notation from 2's complements to sign magnitude
- decode the thermometer MSB, 6 to 64
- provide the sign to the digital isolator
- output parallel data, 81 I/O per channel (162 I/O total)
I have some questions for FPGA experts:
- I assume to use the I2S clock (BCK max: 12.288 MHz for 192kHz/32 bit or 24.576 MHz for 384kHz/32) for FPGA timing to manage I2S receiver and store data in the FIFO. Is that correct?
- Then I assume that the FPGA should run at higher clock to manage the other process. Correct?
- So I have different clock domains inside the FPGA. How can I select the right speed clock to do the other processes?
- The latch clock for the DAC is the most crucial signal to generate. Do you think is it better to generate the latch clock from the FPGA or externally dividing the master clock oscillators (for example using something like a 74AC161 counter)?
- What FPGA do you suggest?
- What mux device to switch between the 2 master clock?
I cannot solder BGA, so to build a prototype I need an FPGA development board. Is there any FPGA dev board with such this I/O (around 200)?
Any tips will be very appreciated.
Thanks